Move encoder specific data to encoder dev_priv

1 files changed, 119 insertions, 114 deletions

diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 42b76b24..6fc0cf4f 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -826,83 +826,84 @@ Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) {
     ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    radeon_tvout_ptr tvout = &radeon_output->tvout;
     int offset, refclk, stds;
 
     if (!info->VBIOS) return FALSE;
 
-    if (info->IsAtomBios) {
+    if (info->IsAtomBios)
         return RADEONGetATOMTVInfo(output);
-    } else {
+    else {
 	offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32);
 	if (offset) {
 	    if (RADEON_BIOS8(offset + 6) == 'T') {
 		switch (RADEON_BIOS8(offset + 7) & 0xf) {
 		case 1:
-		    radeon_output->default_tvStd = TV_STD_NTSC;
+		    tvout->default_tvStd = TV_STD_NTSC;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n");
 		    break;
 		case 2:
-		    radeon_output->default_tvStd = TV_STD_PAL;
+		    tvout->default_tvStd = TV_STD_PAL;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n");
 		    break;
 		case 3:
-		    radeon_output->default_tvStd = TV_STD_PAL_M;
+		    tvout->default_tvStd = TV_STD_PAL_M;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n");
 		    break;
 		case 4:
-		    radeon_output->default_tvStd = TV_STD_PAL_60;
+		    tvout->default_tvStd = TV_STD_PAL_60;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n");
 		    break;
 		case 5:
-		    radeon_output->default_tvStd = TV_STD_NTSC_J;
+		    tvout->default_tvStd = TV_STD_NTSC_J;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n");
 		    break;
 		case 6:
-		    radeon_output->default_tvStd = TV_STD_SCART_PAL;
+		    tvout->default_tvStd = TV_STD_SCART_PAL;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n");
 		    break;
 		default:
-		    radeon_output->default_tvStd = TV_STD_NTSC;
+		    tvout->default_tvStd = TV_STD_NTSC;
 		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n");
 		    break;
 		}
-		radeon_output->tvStd = radeon_output->default_tvStd;
+		tvout->tvStd = tvout->default_tvStd;
 
 		refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3;
 		if (refclk == 0)
-		    radeon_output->TVRefClk = 29.498928713; /* MHz */
+		    tvout->TVRefClk = 29.498928713; /* MHz */
 		else if (refclk == 1)
-		    radeon_output->TVRefClk = 28.636360000;
+		    tvout->TVRefClk = 28.636360000;
 		else if (refclk == 2)
-		    radeon_output->TVRefClk = 14.318180000;
+		    tvout->TVRefClk = 14.318180000;
 		else if (refclk == 3)
-		    radeon_output->TVRefClk = 27.000000000;
+		    tvout->TVRefClk = 27.000000000;
 
-		radeon_output->SupportedTVStds = radeon_output->default_tvStd;
+		tvout->SupportedTVStds = tvout->default_tvStd;
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: ");
 		stds = RADEON_BIOS8(offset + 10) & 0x1f;
 		if (stds & TV_STD_NTSC) {
-		    radeon_output->SupportedTVStds |= TV_STD_NTSC;
+		    tvout->SupportedTVStds |= TV_STD_NTSC;
 		    ErrorF("NTSC ");
 		}
 		if (stds & TV_STD_PAL) {
-		    radeon_output->SupportedTVStds |= TV_STD_PAL;
+		    tvout->SupportedTVStds |= TV_STD_PAL;
 		    ErrorF("PAL ");
 		}
 		if (stds & TV_STD_PAL_M) {
-		    radeon_output->SupportedTVStds |= TV_STD_PAL_M;
+		    tvout->SupportedTVStds |= TV_STD_PAL_M;
 		    ErrorF("PAL-M ");
 		}
 		if (stds & TV_STD_PAL_60) {
-		    radeon_output->SupportedTVStds |= TV_STD_PAL_60;
+		    tvout->SupportedTVStds |= TV_STD_PAL_60;
 		    ErrorF("PAL-60 ");
 		}
 		if (stds & TV_STD_NTSC_J) {
-		    radeon_output->SupportedTVStds |= TV_STD_NTSC_J;
+		    tvout->SupportedTVStds |= TV_STD_NTSC_J;
 		    ErrorF("NTSC-J ");
 		}
 		if (stds & TV_STD_SCART_PAL) {
-		    radeon_output->SupportedTVStds |= TV_STD_SCART_PAL;
+		    tvout->SupportedTVStds |= TV_STD_SCART_PAL;
 		    ErrorF("SCART-PAL");
 		}
 		ErrorF("\n");
@@ -990,11 +991,9 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
     return TRUE;
 }
 
-Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
+Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac)
 {
-    ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    RADEONOutputPrivatePtr radeon_output = output->driver_private;
     int offset, rev, bg, dac;
 
     if (!info->VBIOS) return FALSE;
@@ -1013,29 +1012,29 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
 	    if (rev > 4) {
 		bg = RADEON_BIOS8(offset + 0xc) & 0xf;
 		dac = RADEON_BIOS8(offset + 0xd) & 0xf;
-		radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 
 		bg = RADEON_BIOS8(offset + 0xe) & 0xf;
 		dac = RADEON_BIOS8(offset + 0xf) & 0xf;
-		radeon_output->pal_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 
 		bg = RADEON_BIOS8(offset + 0x10) & 0xf;
 		dac = RADEON_BIOS8(offset + 0x11) & 0xf;
-		radeon_output->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 
 		return TRUE;
 	    } else if (rev > 1) {
 		bg = RADEON_BIOS8(offset + 0xc) & 0xf;
 		dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf;
-		radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 
 		bg = RADEON_BIOS8(offset + 0xd) & 0xf;
 		dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf;
-		radeon_output->pal_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 
 		bg = RADEON_BIOS8(offset + 0xe) & 0xf;
 		dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf;
-		radeon_output->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 
 		return TRUE;
 	    }
@@ -1047,17 +1046,17 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
 	    if (rev < 2) {
 		bg = RADEON_BIOS8(offset + 0x3) & 0xf;
 		dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf;
-		radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
-		radeon_output->pal_tvdac_adj = radeon_output->ps2_tvdac_adj;
-		radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj;
+		tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj;
+		tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj;
 
 		return TRUE;
 	    } else {
 		bg = RADEON_BIOS8(offset + 0x4) & 0xf;
 		dac = RADEON_BIOS8(offset + 0x5) & 0xf;
-		radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
-		radeon_output->pal_tvdac_adj = radeon_output->ps2_tvdac_adj;
-		radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj;
+		tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+		tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj;
+		tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj;
 
 		return TRUE;
 	    }
@@ -1067,19 +1066,17 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
     return FALSE;
 }
 
-Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output)
+Bool
+RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds)
 {
-    ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    radeon_native_mode_ptr native_mode = &lvds->native_mode;
     unsigned long tmp, i;
 
-    if (!info->VBIOS) return FALSE;
-
-    if (info->IsAtomBios)
-	return RADEONGetATOMLVDSInfo(output);
-    else {
+    if (!info->VBIOS)
+	return FALSE;
 
+    if (!info->IsAtomBios) {
 	tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40);
 
 	if (!tmp) {
@@ -1097,14 +1094,14 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output)
 	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		       "Panel ID string: %s\n", stmp);
 
-	    radeon_output->PanelXRes = RADEON_BIOS16(tmp+25);
-	    radeon_output->PanelYRes = RADEON_BIOS16(tmp+27);
+	    native_mode->PanelXRes = RADEON_BIOS16(tmp+25);
+	    native_mode->PanelYRes = RADEON_BIOS16(tmp+27);
 	    xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n",
-		       radeon_output->PanelXRes, radeon_output->PanelYRes);
+		       native_mode->PanelXRes, native_mode->PanelYRes);
 
-	    radeon_output->PanelPwrDly = RADEON_BIOS16(tmp+44);
-	    if (radeon_output->PanelPwrDly > 2000 || radeon_output->PanelPwrDly < 0)
-		radeon_output->PanelPwrDly = 2000;
+	    lvds->PanelPwrDly = RADEON_BIOS16(tmp+44);
+	    if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0)
+		lvds->PanelPwrDly = 2000;
 
 	    /* some panels only work well with certain divider combinations.
 	     */
@@ -1125,35 +1122,36 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output)
 	    for (i = 0; i < 32; i++) {
 		tmp0 = RADEON_BIOS16(tmp+64+i*2);
 		if (tmp0 == 0) break;
-		if ((RADEON_BIOS16(tmp0) == radeon_output->PanelXRes) &&
-		    (RADEON_BIOS16(tmp0+2) == radeon_output->PanelYRes)) {
-		    radeon_output->HBlank     = (RADEON_BIOS16(tmp0+17) -
-					RADEON_BIOS16(tmp0+19)) * 8;
-		    radeon_output->HOverPlus  = (RADEON_BIOS16(tmp0+21) -
-					RADEON_BIOS16(tmp0+19) - 1) * 8;
-		    radeon_output->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8;
-		    radeon_output->VBlank     = (RADEON_BIOS16(tmp0+24) -
-					RADEON_BIOS16(tmp0+26));
-		    radeon_output->VOverPlus  = ((RADEON_BIOS16(tmp0+28) & 0x7ff) -
-					RADEON_BIOS16(tmp0+26));
-		    radeon_output->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11);
-		    radeon_output->DotClock   = RADEON_BIOS16(tmp0+9) * 10;
-		    radeon_output->Flags = 0;
+		if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) &&
+		    (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) {
+		    native_mode->HBlank     = (RADEON_BIOS16(tmp0+17) -
+					       RADEON_BIOS16(tmp0+19)) * 8;
+		    native_mode->HOverPlus  = (RADEON_BIOS16(tmp0+21) -
+					       RADEON_BIOS16(tmp0+19) - 1) * 8;
+		    native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8;
+		    native_mode->VBlank     = (RADEON_BIOS16(tmp0+24) -
+					       RADEON_BIOS16(tmp0+26));
+		    native_mode->VOverPlus  = ((RADEON_BIOS16(tmp0+28) & 0x7ff) -
+					       RADEON_BIOS16(tmp0+26));
+		    native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11);
+		    native_mode->DotClock   = RADEON_BIOS16(tmp0+9) * 10;
+		    native_mode->Flags = 0;
 		}
 	    }
 	}
-    }
 
-    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-	       "LVDS Info:\n"
-	       "XRes: %d, YRes: %d, DotClock: %d\n"
-	       "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n"
-	       "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n",
-	       radeon_output->PanelXRes, radeon_output->PanelYRes, radeon_output->DotClock,
-	       radeon_output->HBlank, radeon_output->HOverPlus, radeon_output->HSyncWidth,
-	       radeon_output->VBlank, radeon_output->VOverPlus, radeon_output->VSyncWidth);
+	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		   "LVDS Info:\n"
+		   "XRes: %d, YRes: %d, DotClock: %d\n"
+		   "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n"
+		   "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n",
+		   native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock,
+		   native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth,
+		   native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth);
 
-    return TRUE;
+	return TRUE;
+    }
+    return FALSE;
 }
 
 xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output)
@@ -1179,11 +1177,9 @@ xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output)
     return mon;
 }
 
-Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
+Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds)
 {
-    ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    RADEONOutputPrivatePtr radeon_output = output->driver_private;
     uint32_t tmp, maxfreq;
     int i, n;
 
@@ -1193,21 +1189,21 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
 	if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) {
 
 	    maxfreq = RADEON_BIOS16(tmp+4);
-	    
+
 	    for (i=0; i<4; i++) {
-		radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6);
+		tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6);
 		/* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */
-		radeon_output->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) |
+		tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) |
 					   ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) |
 					   ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) |
 					   ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16));
-		xf86DrvMsg(pScrn->scrnIndex, X_INFO, 
-			   "TMDS PLL from BIOS: %u %x\n", 
-			   (unsigned)radeon_output->tmds_pll[i].freq,
-			   (unsigned)radeon_output->tmds_pll[i].value);
-		       
-		if (maxfreq == radeon_output->tmds_pll[i].freq) {
-		    radeon_output->tmds_pll[i].freq = 0xffffffff;
+		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+			   "TMDS PLL from BIOS: %u %x\n",
+			   (unsigned)tmds->tmds_pll[i].freq,
+			   (unsigned)tmds->tmds_pll[i].value);
+
+		if (maxfreq == tmds->tmds_pll[i].freq) {
+		    tmds->tmds_pll[i].freq = 0xffffffff;
 		    break;
 		}
 	    }
@@ -1223,8 +1219,8 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
 		n = RADEON_BIOS8(tmp + 5) + 1;
 		if (n > 4) n = 4;
 		for (i=0; i<n; i++) {
-		    radeon_output->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08);
-		    radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10);
+		    tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08);
+		    tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10);
 		}
 		return TRUE;
 	    } else if (RADEON_BIOS8(tmp) == 4) {
@@ -1232,8 +1228,8 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
 		n = RADEON_BIOS8(tmp + 5) + 1;
 		if (n > 4) n = 4;
 		for (i=0; i<n; i++) {
-		    radeon_output->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08);
-		    radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10);
+		    tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08);
+		    tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10);
 		    if (i == 0) stride += 10;
 		    else stride += 6;
 		}
@@ -1288,18 +1284,17 @@ RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id)
     return i2c;
 }
 
-Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
+Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo)
 {
-    ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr info = RADEONPTR(pScrn);
-    RADEONOutputPrivatePtr radeon_output = output->driver_private;
     int offset, table_start, max_freq, gpio_reg, flags;
 
-    if (!info->VBIOS) return FALSE;
+    if (!info->VBIOS)
+	return FALSE;
 
-    if (info->IsAtomBios) {
+    if (info->IsAtomBios)
 	return FALSE;
-    } else if (info->IsIGP) {
+    else if (info->IsIGP) {
 	/* RS4xx TMDS stuff is in the mobile table */
 	offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42);
 	if (offset) {
@@ -1312,7 +1307,7 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
 		    if (offset && (rev > 1)) {
 			int blocks = RADEON_BIOS8(offset + 3);
 			int index = offset + 4;
-			radeon_output->dvo_i2c.valid = FALSE;
+			dvo->dvo_i2c.valid = FALSE;
 			while (blocks > 0) {
 			    int id = RADEON_BIOS16(index);
 			    index += 2;
@@ -1330,10 +1325,10 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
 				index += 2;
 				break;
 			    case 6:
-				radeon_output->dvo_i2c_slave_addr =
+				dvo->dvo_i2c_slave_addr =
 				    RADEON_BIOS16(index) & 0xff;
 				index += 2;
-				radeon_output->dvo_i2c =
+				dvo->dvo_i2c =
 				    RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index));
 				return TRUE;
 			    default:
@@ -1353,17 +1348,17 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
 			RADEON_BIOS8(offset));
 	    table_start = offset+4;
 	    max_freq = RADEON_BIOS16(table_start);
-	    radeon_output->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2);
-	    radeon_output->dvo_i2c.valid = FALSE;
+	    dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2);
+	    dvo->dvo_i2c.valid = FALSE;
 	    gpio_reg = RADEON_BIOS8(table_start+3);
 	    if (gpio_reg == 1)
-		radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
+		dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
 	    else if (gpio_reg == 2)
-		radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+		dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 	    else if (gpio_reg == 3)
-		radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+		dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 	    else if (gpio_reg == 4)
-		radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
+		dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 	    else if (gpio_reg == 5) {
 		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 			   "unsupported MM gpio_reg\n");
@@ -1374,8 +1369,8 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
 		return FALSE;
 	    }
 	    flags = RADEON_BIOS8(table_start+5);
-	    radeon_output->dvo_duallink = flags & 0x01;
-	    if (radeon_output->dvo_duallink) {
+	    dvo->dvo_duallink = flags & 0x01;
+	    if (dvo->dvo_duallink) {
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 			   "Duallink TMDS detected\n");
 	    }
@@ -1394,15 +1389,25 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
     ScrnInfoPtr pScrn = output->scrn;
     RADEONInfoPtr info = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
-    RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+    radeon_dvo_ptr dvo = NULL;
     int offset, index, id;
     uint32_t val, reg, and_mask, or_mask;
 
-    if (!info->VBIOS) return FALSE;
+    if (radeon_encoder == NULL)
+	return FALSE;
 
-    if (info->IsAtomBios) {
+    dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv;
+
+    if (dvo == NULL)
+	return FALSE;
+
+    if (!info->VBIOS)
+	return FALSE;
+
+    if (info->IsAtomBios)
 	return FALSE;
-    } else if (info->IsIGP) {
+    else if (info->IsIGP) {
 	/* RS4xx TMDS stuff is in the mobile table */
 	offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42);
 	if (offset) {
@@ -1459,7 +1464,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
 				index++;
 				ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg,
 				       (unsigned)val);
-				RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
+				RADEONDVOWriteByte(dvo->DVOChip, reg, val);
 				break;
 			    default:
 				ErrorF("unknown id %d\n", id>>13);
@@ -1524,7 +1529,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
 		    index += 1;
 		    ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg,
 			   (unsigned)val);
-		    RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
+		    RADEONDVOWriteByte(dvo->DVOChip, reg, val);
 		    break;
 		default:
 		    ErrorF("unknown id %d\n", id>>13);