R300: First pass at render accel

This first pass is pretty limited.  All it currently supports
is transforms for rotation.  No blending yet.

Based on inital implementation from Wolke Liu with
additional lock-up fixes by Dave Airlie.

1 files changed, 133 insertions, 1 deletions

diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index a1802f86..23a849b7 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -58,7 +58,139 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
     info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
 
     if (info->ChipFamily >= CHIP_FAMILY_R300) {
-	/* Unimplemented */
+	BEGIN_ACCEL(3);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
+	OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(3);
+	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, 0x10011);
+	OUT_ACCEL_REG(R300_GB_SELECT,0x0);
+	OUT_ACCEL_REG(R300_GB_ENABLE, 0x0);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(3);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
+	OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
+	OUT_ACCEL_REG(R300_GB_MSPOS0, 0x78888888);
+	OUT_ACCEL_REG(R300_GB_MSPOS1, 0x08888888);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(4);
+	OUT_ACCEL_REG(R300_GA_POLY_MODE, 0x120);
+	OUT_ACCEL_REG(R300_GA_ROUND_MODE, 0x5);
+	OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, 0xAAAA);
+	OUT_ACCEL_REG(R300_GA_OFFSET, 0x0);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(26);
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
+	OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456);
+	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300);
+	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x6a014001);
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+
+	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
+	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
+	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, 0x2);
+
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(7);
+	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0x0);
+	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0x0);
+	OUT_ACCEL_REG(R300_SU_CULL_MODE, 0x4);
+	OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
+	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0x0);
+	OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
+	OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(R300_US_W_FMT, 0x0);
+	OUT_ACCEL_REG(R300_US_OUT_FMT_1, 0x1B0F);
+	OUT_ACCEL_REG(R300_US_OUT_FMT_2, 0x1B0F);
+	OUT_ACCEL_REG(R300_US_OUT_FMT_3, 0x1B0F);
+	OUT_ACCEL_REG(R300_US_OUT_FMT_0, 0x1B01);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(2);
+	OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0);
+	OUT_ACCEL_REG(R300_RS_INST_0, 0x8);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(12);
+	OUT_ACCEL_REG(R300_US_CONFIG, 0x8);
+	OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
+	OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040);
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0);
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0);
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0);
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
+	OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
+	OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
+	OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
+	OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
+	OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(3);
+	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0x0);
+	OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0x0);
+	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0x0);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(12);
+	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
+	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_ZTOP, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0x0);
+
+	OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, 0xf);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	OUT_ACCEL_REG(R300_RB3D_CCTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0x0);
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+	FINISH_ACCEL();
+
+	BEGIN_ACCEL(7);
+	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
+	OUT_ACCEL_REG(R300_SC_SCISSOR0, 0x0);
+	OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x3ffffff);
+	OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
+	OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
+	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
+	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
+	FINISH_ACCEL();
     } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || 
 	       (info->ChipFamily == CHIP_FAMILY_RV280) || 
 	       (info->ChipFamily == CHIP_FAMILY_RS300) ||