diff options
| author | Alex Deucher <alex@samba.(none)> | 2008-02-27 14:05:44 -0500 |
|---|---|---|
| committer | Alex Deucher <alex@samba.(none)> | 2008-02-27 14:05:44 -0500 |
| commit | b865faf95666e2172c3eec143f77fe9c524e4983 (patch) | |
| tree | 23240e1c99fbf8e40d647173c136c521ced7fb0c /src/radeon_commonfuncs.c | |
| parent | ee485ee0fc550414cd39cdb8fd2769fe0bc996a8 (diff) | |
R100/R200: move r100/r200 specific 3D setup into appropriate blocks
R3xx+ doesn't have these regs.
Diffstat (limited to 'src/radeon_commonfuncs.c')
| -rw-r--r-- | src/radeon_commonfuncs.c | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index 0250aefa..4469cd88 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -239,6 +239,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | R200_VAP_VF_MAX_VTX_NUM); FINISH_ACCEL(); + + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); + OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + FINISH_ACCEL(); } else { BEGIN_ACCEL(2); if ((info->ChipFamily == CHIP_FAMILY_RADEON) || @@ -252,20 +265,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) RADEON_VTX_ST1_NONPARAMETRIC | RADEON_TEX1_W_ROUTING_USE_W0); FINISH_ACCEL(); + + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); + OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + FINISH_ACCEL(); } - BEGIN_ACCEL(5); - OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); - OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); - OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); - OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); - OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | - RADEON_BFACE_SOLID | - RADEON_FFACE_SOLID | - RADEON_VTX_PIX_CENTER_OGL | - RADEON_ROUND_MODE_ROUND | - RADEON_ROUND_PREC_4TH_PIX)); - FINISH_ACCEL(); } |