diff options
| author | Egbert Eich <eich@suse.de> | 2011-11-14 19:10:01 +0100 |
|---|---|---|
| committer | Egbert Eich <eich@freedesktop.org> | 2012-01-05 09:25:48 +0100 |
| commit | ac51e331895b216d288bc7bd108a38b362214668 (patch) | |
| tree | afc04857e82c85fe0d1dc61cec62d659ded03fdf /src/radeon_crtc.c | |
| parent | 0a8d04eeac95f4db9d03ee31070bd825a7feb0b2 (diff) | |
UMS: Fix lockups in palette save/restore on pre-AVIVO chips.
The reintroduction of palette save/restore in 5efdf514 causes some
pre-AVIVO chips to lock up. An investigation revealed that accessing
palette registers when the associated PLL is not running is causing
this. With UMS the PLL setup that is saved has been done by the BIOS
typically.
A similar issue was observed when VGA palette save/restore had
been reinitroduced with 80eee856:
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=480312
and has been worked around for Linux without further investigation
by 87e66ce7.
To fix the issue we now
a. introduce 'on-demand' palette saving (ie the palette is
saved before it is first altered). This guarantees that
the palette register are only associated when the associated
CRTC is active and thus the PLLs are powered up and running.
b. move palette restore before PLL restore.
c. eliminate generic VGA palette save/restore which seems to be
unneeded when the palette is restored natively.
It is believed that this caused the behavior described in
https://bugs.freedesktop.org/show_bug.cgi?id=18407#c27
Signed-off-by: Egbert Eich <eich@freedesktop.org>
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/radeon_crtc.c')
| -rw-r--r-- | src/radeon_crtc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 3c037001..9821ab60 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -510,6 +510,8 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) if (!crtc->enabled) return; + radeon_save_palette_on_demand(pScrn, radeon_crtc->crtc_id); + if (IS_DCE4_VARIANT) { OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |