Add support for allocating PCI GART table in framebuffer memory. This is

    needed to support PCIE Radeons using a new DRM.

1 files changed, 30 insertions, 0 deletions

diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index d302f3e1..8e2fe447 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1969,3 +1969,33 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
     if (info->cursor_start)
 	    xf86ForceHWCursor (pScreen, FALSE);
 }
+
+void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
+{
+    ScrnInfoPtr        pScrn   = xf86Screens[pScreen->myNum];
+    RADEONInfoPtr      info    = RADEONPTR(pScrn);
+    FBAreaPtr fbarea;
+    int width;
+    int height;
+    int width_bytes;
+    int size_bytes;
+
+    if (!info->IsPCI || info->drmMinor<19)
+      return;
+
+    size_bytes = RADEON_PCIGART_TABLE_SIZE;
+    width = pScrn->displayWidth;
+    width_bytes = width * (pScrn->bitsPerPixel / 8);
+    height = (size_bytes + width_bytes - 1)/width_bytes;
+    
+    fbarea = xf86AllocateOffscreenArea(pScreen, width, height, 256, NULL, NULL, NULL);
+
+    if (!fbarea) {
+      xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "PCI GART Table allocation failed due to stupid memory manager\n");
+    } else {
+      info->pciGartSize = size_bytes;
+      info->pciGartOffset = RADEON_ALIGN((fbarea->box.x1 + fbarea->box.y1 * width) *
+					 info->CurrentLayout.pixel_bytes, 256);
+      
+    }
+}