Initial R6xx/R7xx EXA and textured video support

1 files changed, 105 insertions, 93 deletions

diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 968afe69..4520be55 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -45,6 +45,7 @@
 #include "radeon.h"
 #include "radeon_video.h"
 #include "radeon_reg.h"
+#include "r600_reg.h"
 #include "radeon_macros.h"
 #include "radeon_drm.h"
 #include "radeon_dri.h"
@@ -784,92 +785,96 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
     unsigned long mode   = drmAgpGetMode(info->dri->drmFD);	/* Default mode */
     unsigned int  vendor = drmAgpVendorId(info->dri->drmFD);
     unsigned int  device = drmAgpDeviceId(info->dri->drmFD);
-    /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
-       pcie-agp rialto bridge chip - use the one from bridge which must match */
-    uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
-    Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
-    unsigned int defaultMode;
-    MessageType from;
 
-    if (is_v3) {
-	defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
-    } else {
-	if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
-	else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
-	else defaultMode = 1;
-    }
-
-    /* Apply AGPMode Quirks */
-    radeon_agpmode_quirk_ptr p = radeon_agpmode_quirk_list;
-    while (p && p->chipDevice != 0) {
-        if (vendor == p->hostbridgeVendor &&
-            device == p->hostbridgeDevice &&
-            PCI_DEV_VENDOR_ID(info->PciInfo) == p->chipVendor &&
-            PCI_DEV_DEVICE_ID(info->PciInfo) == p->chipDevice &&
-            PCI_SUB_VENDOR_ID(info->PciInfo) == p->subsysVendor &&
-            PCI_SUB_DEVICE_ID(info->PciInfo) == p->subsysDevice)
-        {
-            defaultMode = p->defaultMode;
-        }
-        ++p;
-    }
+    if (info->ChipFamily < CHIP_FAMILY_R600) {
+	/* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
+	   pcie-agp rialto bridge chip - use the one from bridge which must match */
+	uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
+	Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
+	unsigned int defaultMode;
+	MessageType from;
 
-    from = X_DEFAULT;
+	if (is_v3) {
+	    defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
+	} else {
+	    if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
+	    else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
+	    else defaultMode = 1;
+	}
 
-    if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) {
-	if ((info->dri->agpMode < (is_v3 ? 4 : 1)) ||
-            (info->dri->agpMode > (is_v3 ? 8 : 4)) ||
-	    (info->dri->agpMode & (info->dri->agpMode - 1))) {
-	    xf86DrvMsg(pScreen->myNum, X_ERROR,
-		       "Illegal AGP Mode: %d (valid values: %s), leaving at "
-		       "%dx\n", info->dri->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
-		       defaultMode);
-	    info->dri->agpMode = defaultMode;
+	/* Apply AGPMode Quirks */
+	radeon_agpmode_quirk_ptr p = radeon_agpmode_quirk_list;
+	while (p && p->chipDevice != 0) {
+	    if (vendor == p->hostbridgeVendor &&
+		device == p->hostbridgeDevice &&
+		PCI_DEV_VENDOR_ID(info->PciInfo) == p->chipVendor &&
+		PCI_DEV_DEVICE_ID(info->PciInfo) == p->chipDevice &&
+		PCI_SUB_VENDOR_ID(info->PciInfo) == p->subsysVendor &&
+		PCI_SUB_DEVICE_ID(info->PciInfo) == p->subsysDevice)
+	    {
+		defaultMode = p->defaultMode;
+	    }
+	    ++p;
+	}
+
+	from = X_DEFAULT;
+
+	if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) {
+	    if ((info->dri->agpMode < (is_v3 ? 4 : 1)) ||
+		(info->dri->agpMode > (is_v3 ? 8 : 4)) ||
+		(info->dri->agpMode & (info->dri->agpMode - 1))) {
+		xf86DrvMsg(pScreen->myNum, X_ERROR,
+			   "Illegal AGP Mode: %d (valid values: %s), leaving at "
+			   "%dx\n", info->dri->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
+			   defaultMode);
+		info->dri->agpMode = defaultMode;
+	    } else
+		from = X_CONFIG;
 	} else
-	    from = X_CONFIG;
-    } else
-	info->dri->agpMode = defaultMode;
+	    info->dri->agpMode = defaultMode;
 
-    xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->dri->agpMode);
+	xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->dri->agpMode);
 
-    mode &= ~RADEON_AGP_MODE_MASK;
-    if (is_v3) {
-	/* only set one mode bit for AGPv3 */
-	switch (info->dri->agpMode) {
-	case 8:          mode |= RADEON_AGPv3_8X_MODE; break;
-	case 4: default: mode |= RADEON_AGPv3_4X_MODE;
-	}
-	/*TODO: need to take care of other bits valid for v3 mode
-	 *      currently these bits are not used in all tested cards.
-	 */
-    } else {
-	switch (info->dri->agpMode) {
-	case 4:          mode |= RADEON_AGP_4X_MODE;
-	case 2:          mode |= RADEON_AGP_2X_MODE;
-	case 1: default: mode |= RADEON_AGP_1X_MODE;
+	mode &= ~RADEON_AGP_MODE_MASK;
+	if (is_v3) {
+	    /* only set one mode bit for AGPv3 */
+	    switch (info->dri->agpMode) {
+	    case 8:          mode |= RADEON_AGPv3_8X_MODE; break;
+	    case 4: default: mode |= RADEON_AGPv3_4X_MODE;
+	    }
+	    /*TODO: need to take care of other bits valid for v3 mode
+	     *      currently these bits are not used in all tested cards.
+	     */
+	} else {
+	    switch (info->dri->agpMode) {
+	    case 4:          mode |= RADEON_AGP_4X_MODE;
+	    case 2:          mode |= RADEON_AGP_2X_MODE;
+	    case 1: default: mode |= RADEON_AGP_1X_MODE;
+	    }
 	}
-    }
 
-    /* AGP Fast Writes.
-     * TODO: take into account that certain agp modes don't support fast
-     * writes at all */
-    mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
-    if (xf86ReturnOptValBool(info->Options, OPTION_AGP_FW, FALSE)) {
-	xf86DrvMsg(pScreen->myNum, X_WARNING,
-		   "WARNING: Using the AGPFastWrite option is not recommended.\n");
-	xf86Msg(X_NONE, "\tThis option does not provide much of a noticable speed"
-		" boost, while it\n\twill probably hard lock your machine."
-		" All bets are off!\n");
-
-	/* Black list some host/AGP bridges. */
-	if ((vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761))
-	    xf86DrvMsg(pScreen->myNum, X_PROBED, "Ignoring AGPFastWrite option "
-		       "for the AMD 761 northbridge.\n");
-	else {
-	    xf86DrvMsg(pScreen->myNum, X_CONFIG, "Enabling AGP Fast Writes.\n");
-	    mode |= RADEON_AGP_FW_MODE;
-	}
-    } /* Don't mention this otherwise, so that people don't get funny ideas */
+	/* AGP Fast Writes.
+	 * TODO: take into account that certain agp modes don't support fast
+	 * writes at all */
+	mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
+	if (xf86ReturnOptValBool(info->Options, OPTION_AGP_FW, FALSE)) {
+	    xf86DrvMsg(pScreen->myNum, X_WARNING,
+		       "WARNING: Using the AGPFastWrite option is not recommended.\n");
+	    xf86Msg(X_NONE, "\tThis option does not provide much of a noticable speed"
+		    " boost, while it\n\twill probably hard lock your machine."
+		    " All bets are off!\n");
+
+	    /* Black list some host/AGP bridges. */
+	    if ((vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761))
+		xf86DrvMsg(pScreen->myNum, X_PROBED, "Ignoring AGPFastWrite option "
+			   "for the AMD 761 northbridge.\n");
+	    else {
+		xf86DrvMsg(pScreen->myNum, X_CONFIG, "Enabling AGP Fast Writes.\n");
+		mode |= RADEON_AGP_FW_MODE;
+	    }
+	} /* Don't mention this otherwise, so that people don't get funny ideas */
+    } else
+	info->dri->agpMode = 8; /* doesn't matter at this point */
 
     xf86DrvMsg(pScreen->myNum, X_INFO,
 	       "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x 0x%04x/0x%04x]\n",
@@ -904,6 +909,9 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
     ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
     unsigned char *RADEONMMIO = info->MMIO;
 
+    if (info->ChipFamily >= CHIP_FAMILY_R600)
+	return;
+
     /* drm already does this, so we can probably remove this.
      * agp_base_2 ?
      */
@@ -1177,13 +1185,14 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
     drm_radeon_init_t  drmInfo;
 
     memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
-    if ( info->ChipFamily >= CHIP_FAMILY_R300 )
-       drmInfo.func             = RADEON_INIT_R300_CP;
+    if ( info->ChipFamily >= CHIP_FAMILY_R600 )
+	drmInfo.func             = RADEON_INIT_R600_CP;
+    else if ( info->ChipFamily >= CHIP_FAMILY_R300 )
+	drmInfo.func             = RADEON_INIT_R300_CP;
+    else if ( info->ChipFamily >= CHIP_FAMILY_R200 )
+	drmInfo.func		= RADEON_INIT_R200_CP;
     else
-    if ( info->ChipFamily >= CHIP_FAMILY_R200 )
-       drmInfo.func		= RADEON_INIT_R200_CP;
-    else
-       drmInfo.func		= RADEON_INIT_CP;
+	drmInfo.func		= RADEON_INIT_CP;
 
     drmInfo.sarea_priv_offset   = sizeof(XF86DRISAREARec);
     drmInfo.is_pci              = (info->cardType!=CARD_AGP);
@@ -1217,7 +1226,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
      * registers back to their default values, so we need to restore
      * those engine register here.
      */
-    RADEONEngineRestore(pScrn);
+    if (info->ChipFamily < CHIP_FAMILY_R600)
+	RADEONEngineRestore(pScrn);
 
     return TRUE;
 }
@@ -1293,14 +1303,16 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
 		       "[drm] falling back to irq-free operation\n");
 	    info->dri->irq = 0;
 	} else {
-	    unsigned char *RADEONMMIO = info->MMIO;
-	    info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
-
-	    /* Let the DRM know it can safely disable the vblank interrupts */
-	    radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
-				      FALSE);
-	    radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
-				      TRUE);
+	    if (info->ChipFamily < CHIP_FAMILY_R600) {
+		unsigned char *RADEONMMIO = info->MMIO;
+		info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
+
+		/* Let the DRM know it can safely disable the vblank interrupts */
+		radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
+					  FALSE);
+		radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
+					  TRUE);
+	    }
 	}
     }