diff options
| author | Michel Dänzer <michel@tungstengraphics.com> | 2006-12-19 11:19:20 +0100 |
|---|---|---|
| committer | Michel Dänzer <michel@tungstengraphics.com> | 2006-12-19 11:19:20 +0100 |
| commit | 295823d0879a5b574bb79843a6acd43adb9259e5 (patch) | |
| tree | 906690668e8f980f6346bc1268314d27a0fbd0a1 /src/radeon_dri.h | |
| parent | 81f3b4070b70483d6da4f7587e52a64ac69c8ca0 (diff) | |
radeon: Default to leaving AGP transfer mode and fast writes unchanged.
Based on the assumption that firmware should have set up the card and host
bridge appropriately for these settings, this may actually be safer, at least
for the transfer rate; leaving fast writes enabled is hopefully safe as well,
it certainly is on my sytem.
See https://bugs.freedesktop.org/show_bug.cgi?id=9284 .
Diffstat (limited to 'src/radeon_dri.h')
| -rw-r--r-- | src/radeon_dri.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/radeon_dri.h b/src/radeon_dri.h index b4788ca9..6fa7e35d 100644 --- a/src/radeon_dri.h +++ b/src/radeon_dri.h @@ -41,11 +41,6 @@ /* DRI Driver defaults */ #define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO #define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM -/* Default to AGP 4x mode for IGP chips, there are some problems with 1x and 2x - * modes on AGP master side - */ -#define RADEON_DEFAULT_AGP_MODE (info->IsIGP ? 4 : 1) -#define RADEON_DEFAULT_AGP_FAST_WRITE 0 #define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ @@ -55,8 +50,6 @@ #define RADEON_PCIGART_TABLE_SIZE 32768 -#define RADEON_AGP_MAX_MODE 8 - #define RADEON_CARD_TYPE_RADEON 1 #define RADEONCP_USE_RING_BUFFER(m) \ |