diff options
author | Egbert Eich <eich@suse.de> | 2004-03-14 08:33:20 +0000 |
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committer | Egbert Eich <eich@suse.de> | 2004-03-14 08:33:20 +0000 |
commit | 538768e0f472026325be9dd37dc4bfe7ea7d3b75 (patch) | |
tree | 26ddebd0fa3f80fce5b152476aefe1d604f09a88 /src/radeon_driver.c | |
parent | 5f179e796d1cd310790d06eebb474ad67114ec84 (diff) |
Importing vendor version xf86-4_4_99_1 on Sun Mar 14 00:26:39 PST 2004xf86-4_4_99_1
Diffstat (limited to 'src/radeon_driver.c')
-rw-r--r-- | src/radeon_driver.c | 128 |
1 files changed, 110 insertions, 18 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index d190a52e..8f7cd389 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.117 2004/02/19 22:38:12 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.120 2004/03/08 17:12:32 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -5184,7 +5184,6 @@ static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, ~(RADEON_PIX2CLK_SRC_SEL_MASK)); } -#if 0 /* Write palette data */ static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) { @@ -5208,7 +5207,6 @@ static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTPAL_NEXT_CARD32(restore->palette[i]); } } -#endif /* Write out state to define a new video mode */ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) @@ -5277,9 +5275,7 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) } } -#if 0 RADEONRestorePalette(pScrn, &info->SavedReg); -#endif } /* Read common registers */ @@ -5469,7 +5465,7 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONSaveCrtc2Registers(pScrn, save); RADEONSavePLL2Registers(pScrn, save); } - /* RADEONSavePalette(pScrn, save); */ + RADEONSavePalette(pScrn, save); } RADEONTRACE(("RADEONSaveMode returns %p\n", save)); @@ -7031,12 +7027,79 @@ void RADEONFreeScreen(int scrnIndex, int flags) RADEONFreeRec(pScrn); } +/* + * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant). + * + * Note for current DAC mapping when calling this function: + * For most of cards: + * single CRT: Driver doesn't change the existing CRTC->DAC mapping, + * CRTC1 could be driving either DAC or both DACs. + * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC + * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC. + * Some boards have two DACs reversed or don't even have a primary DAC, + * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't + * have a second DAC. + * It's kind of messy, we'll need to redo DAC mapping part some day. + */ +static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + if (IsPrimaryDAC) { + CARD32 dac_cntl; + CARD32 dac_macro_cntl = 0; + dac_cntl = INREG(RADEON_DAC_CNTL); + if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) + dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); + if (IsOn) { + dac_cntl &= ~RADEON_DAC_PDWN; + dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | + RADEON_DAC_PDWN_G | + RADEON_DAC_PDWN_B); + } else { + dac_cntl |= RADEON_DAC_PDWN; + dac_macro_cntl |= (RADEON_DAC_PDWN_R | + RADEON_DAC_PDWN_G | + RADEON_DAC_PDWN_B); + } + OUTREG(RADEON_DAC_CNTL, dac_cntl); + if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) + OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); + } else { + if (info->ChipFamily != CHIP_FAMILY_R200) { + CARD32 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); + if (IsOn) { + tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); + } else { + tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); + } + OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); + } else { + CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); + if (IsOn) { + fp2_gen_cntl |= RADEON_FP2_DV0_EN; + } else { + fp2_gen_cntl &= ~RADEON_FP2_DV0_EN; + } + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + } + } +} + /* Sets VESA Display Power Management Signaling (DPMS) Mode */ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; #ifdef XF86DRI @@ -7055,8 +7118,6 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS); - /* TODO: additional handling for LCD ? */ - switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On; HSync: On, VSync: On */ @@ -7123,13 +7184,19 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, if (info->ChipFamily >= CHIP_FAMILY_R200) { OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); } + } else if (info->DisplayType == MT_CRT) { + RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); } } else { - if ((info->Clone) && (info->CloneType == MT_DFP)) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); + if (info->Clone) { + if (info->CloneType == MT_DFP) { + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); + } + } else if (info->CloneType == MT_CRT) { + RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); } } if (info->DisplayType == MT_DFP) { @@ -7140,6 +7207,14 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON); usleep (info->PanelPwrDly * 1000); OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON); + } else if (info->DisplayType == MT_CRT) { + if ((pRADEONEnt->HasSecondary) || info->Clone) { + RADEONDacPowerSet(pScrn, TRUE, pRADEONEnt->ReversedDAC); + } else { + RADEONDacPowerSet(pScrn, TRUE, TRUE); + if (info->HasCRTC2) + RADEONDacPowerSet(pScrn, TRUE, FALSE); + } } } } else if ((PowerManagementMode == DPMSModeOff) || @@ -7152,13 +7227,19 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, if (info->ChipFamily >= CHIP_FAMILY_R200) { OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); } + } else if (info->DisplayType == MT_CRT) { + RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); } } else { - if ((info->Clone) && (info->CloneType == MT_DFP)) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); + if (info->Clone) { + if(info->CloneType == MT_DFP) { + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); + } + } else if (info->CloneType == MT_CRT) { + RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); } } if (info->DisplayType == MT_DFP) { @@ -7179,6 +7260,17 @@ static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, if (info->IsMobility || info->IsIGP) { OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl); } + } else if (info->DisplayType == MT_CRT) { + if ((pRADEONEnt->HasSecondary) || info->Clone) { + RADEONDacPowerSet(pScrn, FALSE, pRADEONEnt->ReversedDAC); + } else { + /* single CRT, turning both DACs off, we don't really know + * which DAC is actually connected. + */ + RADEONDacPowerSet(pScrn, FALSE, TRUE); + if (info->HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */ + RADEONDacPowerSet(pScrn, FALSE, FALSE); + } } } } |