diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-12-02 18:02:33 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-12-02 18:02:33 -0500 |
| commit | 3a96fbf3b84522cf1ba1b176e82b662222331c14 (patch) | |
| tree | 3203240d8175f8dd2829b1d477e2b39fea3a4d73 /src/radeon_driver.c | |
| parent | f03450796d2e9247a1228c4e2abb1dfad7aecddf (diff) | |
radeon: only read RADEON_PPLL_REF_DIV for ref div on pre-avivo
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/radeon_driver.c')
| -rw-r--r-- | src/radeon_driver.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 5fddcce4..bf560f7d 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1176,20 +1176,21 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) if (RADEONGetClockInfoFromBIOS(pScrn)) { if (pll->reference_div < 2) { /* retrive it from register setting for fitting into current PLL algorithm. - We'll probably need a new routine to calculate the best ref_div from BIOS - provided min_input_pll and max_input_pll + We'll probably need a new routine to calculate the best ref_div from BIOS + provided min_input_pll and max_input_pll */ - uint32_t tmp; - tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; - } else { - pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; + if (!IS_AVIVO_VARIANT) { + uint32_t tmp; + tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_RS400) || + (info->ChipFamily == CHIP_FAMILY_RS480)) { + pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; + } else { + pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; + } } - if (pll->reference_div < 2) pll->reference_div = 12; } } else { |