diff options
| author | Alon Ziv <alonz@nolaviz.org> | 2007-07-30 22:47:59 +0300 |
|---|---|---|
| committer | Michel Dänzer <michel@tungstengraphics.com> | 2007-08-23 12:12:01 +0200 |
| commit | de26e406f52b3b13f03eee2b8023924ec6406f0a (patch) | |
| tree | 8e842e5ded3b28eecb846bd91de5e68a5635ff47 /src/radeon_driver.c | |
| parent | c66e5de26ae93caa368213f3cce139aacec955d2 (diff) | |
radeon: Sane handling of timeouts in WaitForVerticalSync(2).
RADEONWaitForVerticalSync() and RADEONWaitForVerticalSync2() need to wait
for a timeout specified in milliseconds; looping around usleep() causes
the timeout to be unnecessarily long, as the OS may sleep longer than
requested (on Linux the minimum actual sleep value may be several ms).
The new logic uses gettimeofday() in the loop to see when the (absolute)
timeout has arrived.
Signed-off-by: Alon Ziv <alonz@nolaviz.org>
Diffstat (limited to 'src/radeon_driver.c')
| -rw-r--r-- | src/radeon_driver.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 87f14056..469e7bc3 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -724,7 +724,7 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; CARD32 crtc_gen_cntl; - int i; + struct timeval timeout; crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || @@ -735,10 +735,10 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); /* Wait for it to go back up */ - for (i = 0; i < RADEON_TIMEOUT/1000; i++) { - if (INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) break; - usleep(1); - } + radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); + while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && + !radeon_timedout(&timeout)) + usleep(100); } /* Wait for vertical sync on secondary CRTC */ @@ -747,7 +747,7 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; CARD32 crtc2_gen_cntl; - int i; + struct timeval timeout; crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || @@ -758,10 +758,10 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); /* Wait for it to go back up */ - for (i = 0; i < RADEON_TIMEOUT/1000; i++) { - if (INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) break; - usleep(1); - } + radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); + while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && + !radeon_timedout(&timeout)) + usleep(100); } |