diff options
author | Alex Deucher <alex@samba.(none)> | 2008-03-24 14:25:03 -0400 |
---|---|---|
committer | Alex Deucher <alex@samba.(none)> | 2008-03-24 14:25:03 -0400 |
commit | 305a3310963a5dd07b3495015b06aa8c7c4e6b02 (patch) | |
tree | 0bd67569b4fa3d27cb69a6f0f3dffabb55851ef1 /src/radeon_exa_render.c | |
parent | 399b1d405e602c62d6deebea6d7e1f38886cd8e2 (diff) |
R3xx/R5xx: move more VAP, etc. state setup into common init3d() function
Also some minor code cleanups
Diffstat (limited to 'src/radeon_exa_render.c')
-rw-r--r-- | src/radeon_exa_render.c | 315 |
1 files changed, 52 insertions, 263 deletions
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index d968dc89..9496bb66 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -1036,10 +1036,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, CARD32 txenable, colorpitch; CARD32 blendcntl; int pixel_shift; - int has_tcl = 0; /*((info->ChipFamily != CHIP_FAMILY_RS690) && - (info->ChipFamily != CHIP_FAMILY_RS740) && - (info->ChipFamily != CHIP_FAMILY_RS400) && - (info->ChipFamily != CHIP_FAMILY_RV515)); */ ACCEL_PREAMBLE(); TRACE; @@ -1080,234 +1076,49 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, RADEON_SWITCH_TO_3D(); - /* setup the VAP */ - if (has_tcl) { - BEGIN_ACCEL(9); - OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); - OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); - OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (4 << R300_PVS_NUM_FPUS_SHIFT) | - (12 << R300_VF_MAX_VTX_NUM_SHIFT))); - } else { - BEGIN_ACCEL(8); - OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); - OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (4 << R300_PVS_NUM_FPUS_SHIFT) | - (5 << R300_VF_MAX_VTX_NUM_SHIFT))); - } - - OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); - OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); - - if (has_tcl) { - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | - (0 << R300_SKIP_DWORDS_0_SHIFT) | - (0 << R300_DST_VEC_LOC_0_SHIFT) | - R300_SIGNED_0 | - (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | - (0 << R300_SKIP_DWORDS_1_SHIFT) | - (1 << R300_DST_VEC_LOC_1_SHIFT) | - R300_SIGNED_1)); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | - (0 << R300_SKIP_DWORDS_2_SHIFT) | - (2 << R300_DST_VEC_LOC_2_SHIFT) | - R300_LAST_VEC_2 | - R300_SIGNED_2)); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_0_SHIFT) | - (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_1_SHIFT))); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, - ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_2_SHIFT))); - } else { - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | - (0 << R300_SKIP_DWORDS_0_SHIFT) | - (0 << R300_DST_VEC_LOC_0_SHIFT) | - R300_SIGNED_0 | - (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | - (0 << R300_SKIP_DWORDS_1_SHIFT) | - (6 << R300_DST_VEC_LOC_1_SHIFT) | - R300_SIGNED_1)); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | - (0 << R300_SKIP_DWORDS_2_SHIFT) | - (7 << R300_DST_VEC_LOC_2_SHIFT) | - R300_LAST_VEC_2 | - R300_SIGNED_2)); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_0_SHIFT) | - (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_1_SHIFT))); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, - ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) - << R300_WRITE_ENA_2_SHIFT))); - } - FINISH_ACCEL(); - - /* setup the vertex shader */ - if (has_tcl) { - if (pMask) { - BEGIN_ACCEL(22); - /* flush the PVS before updating??? */ - OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); - - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, - ((0 << R300_PVS_FIRST_INST_SHIFT) | - (2 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (2 << R300_PVS_LAST_INST_SHIFT))); - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, - (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); - } else { - BEGIN_ACCEL(18); - /* flush the PVS before updating??? */ - OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); - - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, - ((0 << R300_PVS_FIRST_INST_SHIFT) | - (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (1 << R300_PVS_LAST_INST_SHIFT))); - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, - (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); - } - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); - /* PVS inst 0 */ - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_DST_OPCODE(R300_VE_ADD) | - R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | - R300_PVS_DST_OFFSET(0) | - R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | - R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(0) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(0) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(0) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - - /* PVS inst 1 */ - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_DST_OPCODE(R300_VE_ADD) | - R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | - R300_PVS_DST_OFFSET(1) | - R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | - R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(1) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(1) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(1) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - - if (pMask) { - /* PVS inst 2 */ - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_DST_OPCODE(R300_VE_ADD) | - R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | - R300_PVS_DST_OFFSET(2) | - R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | - R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(2) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(2) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, - (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | - R300_PVS_SRC_OFFSET(2) | - R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | - R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); - } - - OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); - - OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); - FINISH_ACCEL(); - } + BEGIN_ACCEL(8); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, + ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | + (0 << R300_SKIP_DWORDS_0_SHIFT) | + (0 << R300_DST_VEC_LOC_0_SHIFT) | + R300_SIGNED_0 | + (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | + (0 << R300_SKIP_DWORDS_1_SHIFT) | + (6 << R300_DST_VEC_LOC_1_SHIFT) | + R300_SIGNED_1)); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, + ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | + (0 << R300_SKIP_DWORDS_2_SHIFT) | + (7 << R300_DST_VEC_LOC_2_SHIFT) | + R300_LAST_VEC_2 | + R300_SIGNED_2)); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, + ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) + << R300_WRITE_ENA_0_SHIFT) | + (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) + << R300_WRITE_ENA_1_SHIFT))); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, + ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) + << R300_WRITE_ENA_2_SHIFT))); - BEGIN_ACCEL(4); OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | (2 << R300_TEX_1_COMP_CNT_SHIFT))); - OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); + OUT_ACCEL_REG(R300_TX_INVALTAGS, 0); OUT_ACCEL_REG(R300_TX_ENABLE, txenable); FINISH_ACCEL(); @@ -1394,9 +1205,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R300_OUT_FMT_C2_SEL_BLUE | R300_OUT_FMT_C3_SEL_ALPHA); break; - case PICT_r5g6b5: case PICT_a1r5g5b5: case PICT_x1r5g5b5: + /* fix me */ + case PICT_r5g6b5: output_fmt = (R300_OUT_FMT_C_5_6_5 | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | @@ -1567,103 +1379,80 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, CARD32 mask_color, mask_alpha; if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) - //src_color = R300_ALU_RGB_0_0; src_color = (R500_ALU_RGB_R_SWIZ_A_0 | R500_ALU_RGB_G_SWIZ_A_0 | R500_ALU_RGB_B_SWIZ_A_0); else - //src_color = R300_ALU_RGB_SRC0_RGB; src_color = (R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B); if (PICT_FORMAT_A(pSrcPicture->format) == 0) - //src_alpha = R300_ALU_ALPHA_1_0; src_alpha = R500_ALPHA_SWIZ_A_1; else - //src_alpha = R300_ALU_ALPHA_SRC0_A; src_alpha = R500_ALPHA_SWIZ_A_A; if (pMask && pMaskPicture->componentAlpha) { if (RadeonBlendOp[op].src_alpha) { if (PICT_FORMAT_A(pSrcPicture->format) == 0) { - //src_color = R300_ALU_RGB_1_0; - //src_alpha = R300_ALU_ALPHA_1_0; src_color = (R500_ALU_RGB_R_SWIZ_A_1 | R500_ALU_RGB_G_SWIZ_A_1 | R500_ALU_RGB_B_SWIZ_A_1); src_alpha = R500_ALPHA_SWIZ_A_1; } else { - //src_color = R300_ALU_RGB_SRC0_AAA; - //src_alpha = R300_ALU_ALPHA_SRC0_A; src_color = (R500_ALU_RGB_R_SWIZ_A_A | R500_ALU_RGB_G_SWIZ_A_A | R500_ALU_RGB_B_SWIZ_A_A); src_alpha = R500_ALPHA_SWIZ_A_A; } - //mask_color = R300_ALU_RGB_SRC1_RGB; mask_color = (R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B); if (PICT_FORMAT_A(pMaskPicture->format) == 0) - //mask_alpha = R300_ALU_ALPHA_1_0; mask_alpha = R500_ALPHA_SWIZ_B_1; else - //mask_alpha = R300_ALU_ALPHA_SRC1_A; mask_alpha = R500_ALPHA_SWIZ_B_A; } else { - //src_color = R300_ALU_RGB_SRC0_RGB; src_color = (R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B); if (PICT_FORMAT_A(pSrcPicture->format) == 0) - //src_alpha = R300_ALU_ALPHA_1_0; src_alpha = R500_ALPHA_SWIZ_A_1; else - //src_alpha = R300_ALU_ALPHA_SRC0_A; src_alpha = R500_ALPHA_SWIZ_A_A; - //mask_color = R300_ALU_RGB_SRC1_RGB; mask_color = (R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B); if (PICT_FORMAT_A(pMaskPicture->format) == 0) - //mask_alpha = R300_ALU_ALPHA_1_0; mask_alpha = R500_ALPHA_SWIZ_B_1; else - //mask_alpha = R300_ALU_ALPHA_SRC1_A; mask_alpha = R500_ALPHA_SWIZ_B_A; } } else if (pMask) { if (PICT_FORMAT_A(pMaskPicture->format) == 0) - //mask_color = R300_ALU_RGB_1_0; mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1); else - //mask_color = R300_ALU_RGB_SRC1_AAA; mask_color = (R500_ALU_RGB_R_SWIZ_B_A | R500_ALU_RGB_G_SWIZ_B_A | R500_ALU_RGB_B_SWIZ_B_A); if (PICT_FORMAT_A(pMaskPicture->format) == 0) - //mask_alpha = R300_ALU_ALPHA_1_0; mask_alpha = R500_ALPHA_SWIZ_B_1; else - //mask_alpha = R300_ALU_ALPHA_SRC1_A; mask_alpha = R500_ALPHA_SWIZ_B_A; } else { - //mask_color = R300_ALU_RGB_1_0; mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1); - //mask_alpha = R300_ALU_ALPHA_1_0; mask_alpha = R500_ALPHA_SWIZ_B_1; } @@ -1686,9 +1475,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R300_OUT_FMT_C2_SEL_BLUE | R300_OUT_FMT_C3_SEL_ALPHA); break; - case PICT_r5g6b5: case PICT_a1r5g5b5: case PICT_x1r5g5b5: + /* fix me */ + case PICT_r5g6b5: output_fmt = (R300_OUT_FMT_C_5_6_5 | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | @@ -1746,7 +1536,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); - OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6)); + OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); /* src tex */ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | @@ -1798,9 +1588,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | - R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + R500_DY_Q_SWIZ_R)); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | @@ -1833,9 +1623,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | - R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + R500_DY_Q_SWIZ_R)); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); } else { BEGIN_ACCEL(13); OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); @@ -1870,9 +1660,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | - R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + R500_DY_Q_SWIZ_R)); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); } OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | @@ -1916,14 +1706,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, FINISH_ACCEL(); } - BEGIN_ACCEL(4); + BEGIN_ACCEL(3); OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); - OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); FINISH_ACCEL(); |