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authorAlex Deucher <alexander.deucher@amd.com>2012-08-31 18:17:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-28 14:40:56 -0400
commitebc32b27af25b23604e725eb50d844a8d26116bb (patch)
tree767d829df948c656ae7b74a26ccdb02466e4dbd2 /src/radeon_kms.c
parent4adaea996454b1ad5185f9c0f37667dbfc266495 (diff)
radeon: update cursor handling for CIK
CIK asics have 128x128 hw cursors Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'src/radeon_kms.c')
-rw-r--r--src/radeon_kms.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 9783c932..c3f50d59 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -51,9 +51,6 @@
#include "radeon_chipinfo_gen.h"
-#define CURSOR_WIDTH 64
-#define CURSOR_HEIGHT 64
-
#include "radeon_bo_gem.h"
#include "radeon_cs_gem.h"
#include "radeon_vbo.h"
@@ -946,6 +943,15 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
}
}
+ /* set cursor size */
+ if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) {
+ info->cursor_w = CURSOR_WIDTH_CIK;
+ info->cursor_h = CURSOR_HEIGHT_CIK;
+ } else {
+ info->cursor_w = CURSOR_WIDTH;
+ info->cursor_h = CURSOR_HEIGHT;
+ }
+
{
struct drm_radeon_gem_info mminfo;
@@ -1016,7 +1022,10 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
{
- return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
+ ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ return xf86_cursors_init (pScreen, info->cursor_w, info->cursor_h,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
@@ -1532,9 +1541,10 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
info->front_surface = surface;
}
{
- int cursor_size = 64 * 4 * 64;
+ int cursor_size;
int c;
+ cursor_size = info->cursor_w * info->cursor_h * 4;
cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
for (c = 0; c < xf86_config->num_crtc; c++) {
/* cursor objects */