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authorAlex Deucher <alexdeucher@gmail.com>2010-10-27 20:16:17 -0400
committerAlex Deucher <alexdeucher@gmail.com>2010-10-27 20:16:17 -0400
commit040140b5d7cbeaf5d83687bc87e4a236ff9f0cbd (patch)
tree9c17466159944a180ae8f160338c0ca3f7ddc0f9 /src/radeon_kms.c
parentf07f9b7b61c05f2de1d61bb0e2f71bd017c8d36a (diff)
drm/radeon: unify fb bo alignment harder
More duplicated paths discoved...
Diffstat (limited to 'src/radeon_kms.c')
-rw-r--r--src/radeon_kms.c21
1 files changed, 16 insertions, 5 deletions
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index e2406075..642e4917 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -528,6 +528,8 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
DevUnion* pPriv;
Gamma zeros = { 0.0, 0.0, 0.0 };
Bool colorTilingDefault;
+ uint32_t tiling = 0;
+ int cpp;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONPreInit_KMS\n");
@@ -671,7 +673,16 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
else
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"EXA: Driver will not allow EXA pixmaps in VRAM\n");
- RADEONSetPitch(pScrn);
+
+ /* no tiled scanout on r6xx+ yet */
+ if (info->allowColorTiling) {
+ if (info->ChipFamily < CHIP_FAMILY_R600)
+ tiling |= RADEON_TILING_MACRO;
+ }
+ cpp = pScrn->bitsPerPixel / 8;
+ pScrn->displayWidth =
+ RADEON_ALIGN(pScrn->virtualX * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling)) / cpp;
+ info->CurrentLayout.displayWidth = pScrn->displayWidth;
/* Set display resolution */
xf86SetDpi(pScrn, 0, 0);
@@ -1088,7 +1099,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
int screen_size;
- int stride;
+ int pitch;
int total_size_bytes = 0, remain_size_bytes;
uint32_t tiling_flags = 0;
@@ -1107,8 +1118,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
if (info->ChipFamily < CHIP_FAMILY_R600)
tiling_flags |= RADEON_TILING_MACRO;
}
- stride = RADEON_ALIGN(pScrn->displayWidth * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling_flags));
- screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * stride;
+ pitch = RADEON_ALIGN(pScrn->displayWidth * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling_flags));
+ screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
{
int cursor_size = 64 * 4 * 64;
int c;
@@ -1168,7 +1179,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
#endif
if (tiling_flags) {
radeon_bo_set_tiling(info->front_bo,
- tiling_flags | RADEON_TILING_SURFACE, stride);
+ tiling_flags | RADEON_TILING_SURFACE, pitch);
}
}