diff options
| author | Dave Airlie <airlied@redhat.com> | 2009-06-30 16:24:37 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-06-30 16:32:01 +1000 |
| commit | e932836691aeaec37794fdaed2dabb22710fd171 (patch) | |
| tree | 078de611599b48afe5b6cc3d52175004bc8a3662 /src/radeon_macros.h | |
| parent | bb04b450ed00ca4b1aa44c33085567d47b33b547 (diff) | |
radeon: initial preparation for kms patch.
This patch contains most of the changes to the EXA and texture video
accel code.
It adds a few bits of pixmap support but doesn't actually do anything
useful KMS yet.
Testing this should not have any regressions over what we have already,
biggest worries are r6xx, I've fixed a textured video one, but no idea
what other might lurk
It won't build against libdrm radeon yet either
Diffstat (limited to 'src/radeon_macros.h')
| -rw-r--r-- | src/radeon_macros.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/radeon_macros.h b/src/radeon_macros.h index 8575884c..15d9d73a 100644 --- a/src/radeon_macros.h +++ b/src/radeon_macros.h @@ -160,4 +160,41 @@ do { \ #define INPCIE_P(pScrn, addr) R600INPCIE_PORT(pScrn, addr) #define OUTPCIE_P(pScrn, addr, val) R600OUTPCIE_PORT(pScrn, addr, val) +#define BEGIN_ACCEL_RELOC(n, r) do { \ + int _nqw = (n) + (info->cs ? (r) : 0); \ + BEGIN_ACCEL(_nqw); \ + } while (0) + +#define CHECK_OFFSET(pPix, mask, type) do { \ + if (!info->cs) { \ + uint32_t _pix_offset = radeonGetPixmapOffset(pPix); \ + if ((_pix_offset & mask) != 0) \ + RADEON_FALLBACK(("Bad %s offset 0x%x\n", type, (int)pix_offset)); \ + } \ + } while(0) + +#define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \ + if (info->cs) { \ + driver_priv = exaGetPixmapDriverPrivate(pPix); \ + OUT_ACCEL_REG((reg), 0); \ + OUT_RELOC(driver_priv->bo, (rd), (wd)); \ + } else { \ + uint32_t _pix_offset; \ + _pix_offset = radeonGetPixmapOffset(pPix); \ + OUT_ACCEL_REG((reg), _pix_offset | value); \ + } \ + } while(0) + +#define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0) +#define EMIT_WRITE_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, 0, RADEON_GEM_DOMAIN_VRAM) + +#define OUT_TEXTURE_REG(reg, offset, bo) do { \ + if (info->cs) { \ + OUT_ACCEL_REG((reg), (offset)); \ + OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \ + } else { \ + OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \ + } while(0) + + #endif |