Fix RN50 mode filtering.

The old code would attempt to limit the maximum pixel size of the screen
by limiting the maximum PLL frequency.  This ends up confusing the PLL
computation code since sometimes your maximum freq can be lower than your
minimum freq.  More to the point it's just wrong, maximum PLL frequency
isn't the same thing as maximum pixel clock, and even that isn't the same
thing as maximum scanout pixels per second.

The correct thing to do is filter by the mode's effective memory bandwidth.

1 files changed, 13 insertions, 0 deletions

diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9850702c..64c0438d 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -789,6 +789,19 @@ static int
 radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
 {
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    ScrnInfoPtr pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+    /*
+     * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+     * XXX should really do this for all chips by properly computing
+     * memory bandwidth and an overhead factor.
+     */
+    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+	if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300)
+	    return MODE_BANDWIDTH;
+    }
 
     if (radeon_output->type == OUTPUT_STV ||
 	radeon_output->type == OUTPUT_CTV) {