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| author | Alexander Gottwald <alexander.gottwald@s1999.tu-chemnitz.de> | 2004-03-17 20:30:34 +0000 |
|---|---|---|
| committer | Alexander Gottwald <alexander.gottwald@s1999.tu-chemnitz.de> | 2004-03-17 20:30:34 +0000 |
| commit | c52d418593a27c95a12c53051aec2998d688476a (patch) | |
| tree | 1ca0d1f1b36f523b690c06fcbca30179053d1d28 /src/radeon_reg.h | |
| parent | 2eab4a4e2b8f2ec2154738f0dd57cf0dc5c7816a (diff) | |
merge with XORG-RELEASE-1 (tag XORG-CYGWIN-LAST-MERGE)CYGWIN-RELEASE-1-MERGE
Diffstat (limited to 'src/radeon_reg.h')
| -rw-r--r-- | src/radeon_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 1d73e214..8af5da5c 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -65,6 +65,12 @@ # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_STATUS_PCI_CONFIG 0x06 +# define RADEON_CAP_LIST 0x100000 +#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ +# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ +# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ +# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ # define RADEON_AGP_ENABLE (1<<8) @@ -401,11 +407,16 @@ # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 # define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_DAC_MACRO_CNTL 0x0d04 +# define RADEON_DAC_PDWN_R (1 << 16) +# define RADEON_DAC_PDWN_G (1 << 17) +# define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_STD_MASK 0x0300 # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) +# define RADEON_TV_DAC_BGSLEEP (1 << 26) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 @@ -1064,6 +1075,8 @@ # define RADEON_SURF_TRANSLATION_DIS (1 << 8) # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_INFO 0x0b0c #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 |