DRI XFree86-4_3_99_12-merge importDRI-XFree86-4_3_99_12-merge

1 files changed, 7 insertions, 53 deletions

diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 8af5da5c..73b5da16 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.31 2003/11/10 18:41:23 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.28 2003/07/02 17:31:30 martin Exp $ */
 /*
  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  *                VA Linux Systems Inc., Fremont, California.
@@ -65,15 +65,7 @@
 #       define RADEON_AGP_APER_SIZE_8MB     (0x3e << 0)
 #       define RADEON_AGP_APER_SIZE_4MB     (0x3f << 0)
 #       define RADEON_AGP_APER_SIZE_MASK    (0x3f << 0)
-#define RADEON_STATUS_PCI_CONFIG            0x06
-#       define RADEON_CAP_LIST              0x100000
-#define RADEON_CAPABILITIES_PTR_PCI_CONFIG  0x34 /* offset in PCI config*/
-#       define RADEON_CAP_PTR_MASK          0xfc /* mask off reserved bits of CAP_PTR */
-#       define RADEON_CAP_ID_NULL           0x00 /* End of capability list */
-#       define RADEON_CAP_ID_AGP            0x02 /* AGP capability ID */
 #define RADEON_AGP_COMMAND                  0x0f60 /* PCI */
-#define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/
-#       define RADEON_AGP_ENABLE            (1<<8)
 #define RADEON_AGP_PLL_CNTL                 0x000b /* PLL */
 #define RADEON_AGP_STATUS                   0x0f5c /* PCI */
 #       define RADEON_AGP_1X_MODE           0x01
@@ -241,27 +233,9 @@
 #define RADEON_CRC_CMDFIFO_ADDR             0x0740
 #define RADEON_CRC_CMDFIFO_DOUT             0x0744
 #define RADEON_GRPH_BUFFER_CNTL             0x02f0
-#       define RADEON_GRPH_START_REQ_MASK          (0x7f)
-#       define RADEON_GRPH_START_REQ_SHIFT         0
-#       define RADEON_GRPH_STOP_REQ_MASK           (0x7f<<8)
-#       define RADEON_GRPH_STOP_REQ_SHIFT          8
-#       define RADEON_GRPH_CRITICAL_POINT_MASK     (0x7f<<16)
-#       define RADEON_GRPH_CRITICAL_POINT_SHIFT    16
-#       define RADEON_GRPH_CRITICAL_CNTL           (1<<28)
-#       define RADEON_GRPH_BUFFER_SIZE             (1<<29)
-#       define RADEON_GRPH_CRITICAL_AT_SOF         (1<<30)
-#       define RADEON_GRPH_STOP_CNTL               (1<<31)
+#       define GRPH_CRITICAL_POINT_MASK     (0x7f<<16)
 #define RADEON_GRPH2_BUFFER_CNTL            0x03f0
-#       define RADEON_GRPH2_START_REQ_MASK         (0x7f)
-#       define RADEON_GRPH2_START_REQ_SHIFT         0
-#       define RADEON_GRPH2_STOP_REQ_MASK          (0x7f<<8)
-#       define RADEON_GRPH2_STOP_REQ_SHIFT         8
-#       define RADEON_GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)
-#       define RADEON_GRPH2_CRITICAL_POINT_SHIFT   16
-#       define RADEON_GRPH2_CRITICAL_CNTL          (1<<28)
-#       define RADEON_GRPH2_BUFFER_SIZE            (1<<29)
-#       define RADEON_GRPH2_CRITICAL_AT_SOF        (1<<30)
-#       define RADEON_GRPH2_STOP_CNTL              (1<<31)
+#       define GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)
 #define RADEON_CRTC_CRNT_FRAME              0x0214
 #define RADEON_CRTC_EXT_CNTL                0x0054
 #       define RADEON_CRTC_VGA_XOVERSCAN    (1 <<  0)
@@ -303,8 +277,7 @@
 #       define RADEON_CRTC2_HSYNC_DIS       (1 << 28)
 #       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)
 #define RADEON_CRTC_MORE_CNTL               0x27c
-#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
-#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
+#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)   
 #define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
 #define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
 #       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
@@ -407,16 +380,11 @@
 #       define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
 #       define RADEON_DAC_FORCE_DATA_MASK   0x0003ff00
 #       define RADEON_DAC_FORCE_DATA_SHIFT  8
-#define RADEON_DAC_MACRO_CNTL               0x0d04
-#       define RADEON_DAC_PDWN_R            (1 << 16)
-#       define RADEON_DAC_PDWN_G            (1 << 17)
-#       define RADEON_DAC_PDWN_B            (1 << 18)
 #define RADEON_TV_DAC_CNTL                  0x088c
 #       define RADEON_TV_DAC_STD_MASK       0x0300
 #       define RADEON_TV_DAC_RDACPD         (1 <<  24)
 #       define RADEON_TV_DAC_GDACPD         (1 <<  25)
 #       define RADEON_TV_DAC_BDACPD         (1 <<  26)
-#       define RADEON_TV_DAC_BGSLEEP        (1 <<  26)
 #define RADEON_DISP_HW_DEBUG                0x0d14
 #       define RADEON_CRT2_DISP1_SEL        (1 <<  5)
 #define RADEON_DISP_OUTPUT_CNTL             0x0d64
@@ -441,7 +409,7 @@
 #define RADEON_DEVICE_ID                    0x0f02 /* PCI */
 #define RADEON_DISP_MISC_CNTL               0x0d00
 #       define RADEON_SOFT_RESET_GRPH_PP    (1 << 0)
-#define RADEON_DISP_MERGE_CNTL		  0x0d60
+#define RADEON_DISP_MERGE_CNTL	          0x0d60
 #       define RADEON_DISP_ALPHA_MODE_MASK  0x03
 #       define RADEON_DISP_ALPHA_MODE_KEY   0
 #       define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
@@ -450,7 +418,7 @@
 #       define RADEON_DISP_GRPH_ALPHA_MASK  (0xff << 16)
 #       define RADEON_DISP_OV0_ALPHA_MASK   (0xff << 24)
 #	define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
-#define RADEON_DISP2_MERGE_CNTL		    0x0d68
+#define RADEON_DISP2_MERGE_CNTL	            0x0d68
 #       define RADEON_DISP2_RGB_OFFSET_EN   (1<<8)
 #define RADEON_DISP_LIN_TRANS_GRPH_A        0x0d80
 #define RADEON_DISP_LIN_TRANS_GRPH_B        0x0d84
@@ -786,12 +754,6 @@
 #define RADEON_MEM_ADDR_CONFIG              0x0148
 #define RADEON_MEM_BASE                     0x0f10 /* PCI */
 #define RADEON_MEM_CNTL                     0x0140
-#       define RADEON_MEM_NUM_CHANNELS_MASK 0x01
-#       define RADEON_MEM_USE_B_CH_ONLY     (1<<1)
-#       define RV100_HALF_MODE              (1<<3)
-#       define R300_MEM_NUM_CHANNELS_MASK   0x03
-#       define R300_MEM_USE_CD_CH_ONLY      (1<<2)
-#define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
 #define RADEON_MEM_INIT_LAT_TIMER           0x0154
 #define RADEON_MEM_INTF_CNTL                0x014c
 #define RADEON_MEM_SDRAM_MODE_REG           0x0158
@@ -804,13 +766,7 @@
 #define RADEON_MPLL_CNTL                    0x000e /* PLL */
 #define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */
 #define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */
-#define R300_MC_IND_INDEX                   0x01f8
-#       define R300_MC_IND_ADDR_MASK        0x3f
-#define R300_MC_IND_DATA                    0x01fc
-#define R300_MC_READ_CNTL_AB                0x017c
-#       define R300_MEM_RBS_POSITION_A_MASK 0x03
-#define R300_MC_READ_CNTL_CD_mcind	    0x24
-#       define R300_MEM_RBS_POSITION_C_MASK 0x03
+
 
 #define RADEON_N_VIF_COUNT                  0x0248
 
@@ -1075,8 +1031,6 @@
 #       define RADEON_SURF_TRANSLATION_DIS  (1 << 8)
 #       define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
 #       define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
-#       define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
-#       define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
 #define RADEON_SURFACE0_INFO                0x0b0c
 #define RADEON_SURFACE0_LOWER_BOUND         0x0b04
 #define RADEON_SURFACE0_UPPER_BOUND         0x0b08