diff options
| author | Alex Deucher <alex@samba.(none)> | 2008-03-21 16:21:54 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@samba.(none)> | 2008-03-21 16:21:54 -0400 |
| commit | 6d5066a451017a2683addc9e2496987626795dda (patch) | |
| tree | a23111f938b5b8f7c7a2553d45eb8b07b47ee1ec /src/radeon_reg.h | |
| parent | fb1cffac05ae20c8365b25a2042b0ae961880faf (diff) | |
RS4xx: attempt to set up disp/disp2 fifos correctly
If you have an XPRESS chip, please test!!!
Diffstat (limited to 'src/radeon_reg.h')
| -rw-r--r-- | src/radeon_reg.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 6a3d964f..dcfdbac0 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3356,9 +3356,31 @@ # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) #define RS400_DISP2_REQ_CNTL1 0xe30 +# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff #define RS400_DISP2_REQ_CNTL2 0xe34 +# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff #define RS400_DMIF_MEM_CNTL1 0xe38 +# define RS400_DISP2_START_ADR_SHIFT 0 +# define RS400_DISP2_START_ADR_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff #define RS400_DISP1_REQ_CNTL1 0xe3c +# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff |