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authorMaciej Cencora <m.cencora@gmail.com>2007-09-20 23:56:08 -0400
committerAlex Deucher <alex@botch2.(none)>2007-09-20 23:56:08 -0400
commit5a6f74103f0ec0d451d0e2573442efe5922848af (patch)
tree2df1f261f81169b366e39e45acb0a08174b8d27e /src/radeon_vip.c
parentc72a365386e19f9257db041d44b09ad499cc9f6a (diff)
RADEON: fix video in on RV380 (tested on X600 VIVO)
Diffstat (limited to 'src/radeon_vip.c')
-rw-r--r--src/radeon_vip.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/radeon_vip.c b/src/radeon_vip.c
index abcba06a..7ee4ab5b 100644
--- a/src/radeon_vip.c
+++ b/src/radeon_vip.c
@@ -331,6 +331,13 @@ void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
+ case CHIP_FAMILY_RV380:
+ OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
+ OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
+ OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
+ OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
+ OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
+ break;
default:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);