diff options
| author | David Miller <davem@davemloft.net> | 2009-02-15 18:26:14 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2009-02-15 18:27:04 +1000 |
| commit | 00ac9d2f8d58725d0d3e6b1bf7f728d9ae7e6109 (patch) | |
| tree | a78466478193508829b1fba2b7c157c8a81f954f /src | |
| parent | 2de90c8349409eb892edc57fd24b61b679eb7719 (diff) | |
GART: Save/restore GART table consistently.
Always save the GART table with the RADEON_SURFACE_CNTL register
zero'd out to make sure we always use the same endinanness.
fixed up as per Michel's suggestion for endianness.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'src')
| -rw-r--r-- | src/radeon_driver.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 813b25e0..d22db58d 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -5511,8 +5511,17 @@ Bool RADEONEnterVT(int scrnIndex, int flags) if (info->cardType == CARD_PCIE && info->dri->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) { +#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); + /* we need to backup the PCIE GART TABLE from fb memory */ + OUTREG(RADEON_SURFACE_CNTL, 0); +#endif memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); +#if X_BYTE_ORDER == X_BIG_ENDIAN + OUTREG(RADEON_SURFACE_CNTL, sctrl); +#endif } /* get the DRI back into shape after resume */ @@ -5562,8 +5571,17 @@ void RADEONLeaveVT(int scrnIndex, int flags) if (info->cardType == CARD_PCIE && info->dri->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) { +#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); + /* we need to backup the PCIE GART TABLE from fb memory */ + OUTREG(RADEON_SURFACE_CNTL, 0); +#endif memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); +#if X_BYTE_ORDER == X_BIG_ENDIAN + OUTREG(RADEON_SURFACE_CNTL, sctrl); +#endif } /* Make sure 3D clients will re-upload textures to video RAM */ |