6xx/7xx: clean up gpr/const handling in shaders

2 files changed, 105 insertions, 101 deletions

diff --git a/src/r600_shader.c b/src/r600_shader.c
index b42690c9..7dceffec 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -157,11 +157,11 @@ int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 					       BARRIER(1));
 
     /* 2 */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_X),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_X),
 			     SRC1_NEG(0),
@@ -183,11 +183,11 @@ int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 DST_ELEM(ELEM_X),
 				 CLAMP(1));
     /* 3 */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_Y),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_Y),
 			     SRC1_NEG(0),
@@ -209,11 +209,11 @@ int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 DST_ELEM(ELEM_Y),
 				 CLAMP(1));
     /* 4 */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_Z),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_Z),
 			     SRC1_NEG(0),
@@ -235,11 +235,11 @@ int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 DST_ELEM(ELEM_Z),
 				 CLAMP(1));
     /* 5 */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_W),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_W),
 			     SRC1_NEG(0),
@@ -522,11 +522,11 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
 
 
     /* 4 texX / w */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -549,11 +549,11 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 5 texY / h */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -690,18 +690,18 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                                BARRIER(1));
     /* 4,5,6,7 */
     /* r2.x = MAD(c0.w, r1.x, c0.x) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
                              INDEX_MODE(SQ_INDEX_LOOP),
                              PRED_SEL(SQ_PRED_SEL_OFF),
                              LAST(0));
-    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(256),
+    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
                                  SRC2_REL(ABSOLUTE),
                                  SRC2_ELEM(ELEM_X),
                                  SRC2_NEG(0),
@@ -712,18 +712,18 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_X),
                                  CLAMP(0));
     /* r2.y = MAD(c0.w, r1.x, c0.y) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
                              INDEX_MODE(SQ_INDEX_LOOP),
                              PRED_SEL(SQ_PRED_SEL_OFF),
                              LAST(0));
-    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(256),
+    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
                                  SRC2_REL(ABSOLUTE),
                                  SRC2_ELEM(ELEM_Y),
                                  SRC2_NEG(0),
@@ -734,18 +734,18 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_Y),
                                  CLAMP(0));
     /* r2.z = MAD(c0.w, r1.x, c0.z) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(256),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
                              INDEX_MODE(SQ_INDEX_LOOP),
                              PRED_SEL(SQ_PRED_SEL_OFF),
                              LAST(0));
-    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(256),
+    shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
                                  SRC2_REL(ABSOLUTE),
                                  SRC2_ELEM(ELEM_Z),
                                  SRC2_NEG(0),
@@ -780,11 +780,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 
     /* 8,9,10,11 */
     /* r2.x = MAD(c1.x, r1.y, pv.x) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(257),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -802,11 +802,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_X),
                                  CLAMP(0));
     /* r2.y = MAD(c1.y, r1.y, pv.y) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(257),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -824,11 +824,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_Y),
                                  CLAMP(0));
     /* r2.z = MAD(c1.z, r1.y, pv.z) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(257),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -869,11 +869,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
     /* 12,13,14,15 */
     /* r2.x = MAD(c2.x, r1.z, pv.x) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(258),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -891,11 +891,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_X),
                                  CLAMP(1));
     /* r2.y = MAD(c2.y, r1.z, pv.y) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(258),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -913,11 +913,11 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_ELEM(ELEM_Y),
                                  CLAMP(1));
     /* r2.z = MAD(c2.z, r1.z, pv.z) */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(258),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(1),
+                             SRC1_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1361,11 +1361,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
 
 
     /* 14 srcX.x DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -1388,11 +1388,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 15 srcX.y DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -1415,11 +1415,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 16 srcX.z DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1442,11 +1442,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 17 srcX.w DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1469,11 +1469,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 18 srcY.x DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -1496,11 +1496,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 19 srcY.y DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -1523,11 +1523,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 20 srcY.z DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1550,11 +1550,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 21 srcY.w DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1577,11 +1577,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 22 maskX.x DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(258),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -1604,11 +1604,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 23 maskX.y DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(258),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -1631,11 +1631,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 24 maskX.z DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(258),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1658,11 +1658,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 25 maskX.w DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(258),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1685,11 +1685,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 26 maskY.x DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(259),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 3),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -1712,11 +1712,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 27 maskY.y DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(259),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 3),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -1739,11 +1739,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 28 maskY.z DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(259),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 3),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1766,11 +1766,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 29 maskY.w DOT4 - mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(259),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 3),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1793,11 +1793,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 30 srcX / w */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(3),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1820,11 +1820,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 31 srcY / h */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(3),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1847,11 +1847,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 32 maskX / w */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(4),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(258),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 2),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1874,11 +1874,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 33 maskY / h */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(4),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(259),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 3),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -1901,11 +1901,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 34 srcX.x DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -1928,11 +1928,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 35 srcX.y DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -1955,11 +1955,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 36 srcX.z DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -1982,11 +1982,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 37 srcX.w DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -2009,11 +2009,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 38 srcY.x DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_X),
                              SRC1_NEG(0),
@@ -2036,11 +2036,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 39 srcY.y DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Y),
                              SRC1_NEG(0),
@@ -2063,11 +2063,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 40 srcY.z DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Z),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_Z),
                              SRC1_NEG(0),
@@ -2090,11 +2090,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 41 srcY.w DOT4 - non-mask */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(0),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_W),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -2117,11 +2117,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 42 srcX / w */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(2),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_X),
                              SRC0_NEG(0),
-                             SRC1_SEL(256),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 0),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -2144,11 +2144,11 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  CLAMP(0));
 
     /* 43 srcY / h */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(2),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2),
                              SRC0_REL(ABSOLUTE),
                              SRC0_ELEM(ELEM_Y),
                              SRC0_NEG(0),
-                             SRC1_SEL(257),
+                             SRC1_SEL(ALU_SRC_CFILE_BASE + 1),
                              SRC1_REL(ABSOLUTE),
                              SRC1_ELEM(ELEM_W),
                              SRC1_NEG(0),
@@ -2445,11 +2445,11 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 
     /* 10 - alu 0 */
     /* MUL gpr[2].x gpr[1].x gpr[0].x */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_X),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_X),
 			     SRC1_NEG(0),
@@ -2472,11 +2472,11 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 CLAMP(1));
     /* 11 - alu 1 */
     /* MUL gpr[2].y gpr[1].y gpr[0].y */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_Y),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_Y),
 			     SRC1_NEG(0),
@@ -2499,11 +2499,11 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 CLAMP(1));
     /* 12 - alu 2 */
     /* MUL gpr[2].z gpr[1].z gpr[0].z */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_Z),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_Z),
 			     SRC1_NEG(0),
@@ -2526,11 +2526,11 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
 				 CLAMP(1));
     /* 13 - alu 3 */
     /* MUL gpr[2].w gpr[1].w gpr[0].w */
-    shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+    shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
 			     SRC0_REL(ABSOLUTE),
 			     SRC0_ELEM(ELEM_W),
 			     SRC0_NEG(0),
-			     SRC1_SEL(0),
+			     SRC1_SEL(ALU_SRC_GPR_BASE + 0),
 			     SRC1_REL(ABSOLUTE),
 			     SRC1_ELEM(ELEM_W),
 			     SRC1_NEG(0),
diff --git a/src/r600_shader.h b/src/r600_shader.h
index a68d6c2f..3d5acc74 100644
--- a/src/r600_shader.h
+++ b/src/r600_shader.h
@@ -193,6 +193,10 @@
 // 128-159 kcache constants bank 0
 // 160-191 kcache constants bank 1
 // 248-255 special SQ_ALU_SRC_* (0, 1, etc.)
+#define ALU_SRC_GPR_BASE        0
+#define ALU_SRC_KCACHE0_BASE  128
+#define ALU_SRC_KCACHE1_BASE  160
+#define ALU_SRC_CFILE_BASE    256
 
 #define SRC0_REL(x)        (x)
 #define SRC1_REL(x)        (x)