diff options
author | Alex Deucher <alex@botch2.(none)> | 2007-12-21 15:40:18 -0500 |
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committer | Alex Deucher <alex@botch2.(none)> | 2007-12-21 15:40:18 -0500 |
commit | 0631a23bd103f9b74e525da2c41304eab60c6f17 (patch) | |
tree | be2589e0b0b61b8c033b7c5e5c0681e62f0567ea /src | |
parent | 5b917797a13c6caa80028d1842a284598e874288 (diff) |
RADEON: fix rn50 reversion from last merge
Diffstat (limited to 'src')
-rw-r--r-- | src/radeon_driver.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index e65e446e..85cfe88e 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1222,18 +1222,6 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) info->mclk = 200.00; } - if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { - /* Avoid RN50 corruption due to memory bandwidth starvation. - * 18 is an empirical value based on the databook and Windows driver. - * - * Empirical value changed to 24 to raise pixel clock limit and - * allow higher resolution modes on capable monitors - */ - pll->pll_out_max = min(pll->pll_out_max, - 24 * info->mclk * 100 / pScrn->bitsPerPixel * - info->RamWidth / 16); - } - /* card limits for computing PLLs */ if (IS_AVIVO_VARIANT) { pll->min_post_div = 2; |