diff options
author | Marc Aurele La France <tsi@xfree86.org> | 2006-07-29 01:00:56 +0300 |
---|---|---|
committer | George Sapountzis <gsap7@yahoo.gr> | 2006-07-29 01:00:56 +0300 |
commit | 7800407a2db4b7307192bf3b43fffb9c4748b9c0 (patch) | |
tree | 97c90ce49f10f520f1d76672fded9e31578d417d /src | |
parent | 49b11c540d37152eee4907ab30353ede01e4fb56 (diff) |
Bug #807: invalidate read-back cache.
Fix corruption when scaling 1-pixel wide pixmaps, in which case the first CPU
read of the framebuffer will return stale data.
This bug always manifests itself in mach64 EXA (to be committed soon), with
this patch mach64 EXA passes rendercheck.
Diffstat (limited to 'src')
-rw-r--r-- | src/atimach64.c | 3 | ||||
-rw-r--r-- | src/atimach64accel.c | 24 | ||||
-rw-r--r-- | src/atiregs.h | 13 | ||||
-rw-r--r-- | src/atistruct.h | 2 |
4 files changed, 37 insertions, 5 deletions
diff --git a/src/atimach64.c b/src/atimach64.c index 166aaf0c..2cdec787 100644 --- a/src/atimach64.c +++ b/src/atimach64.c @@ -183,6 +183,7 @@ ATIMach64PreInit if (pATI->Chip >= ATI_CHIP_264VTB) { + pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE; pATIHW->mem_cntl = (pATI->LockData.mem_cntl & ~(CTL_MEM_LOWER_APER_ENDIAN | CTL_MEM_UPPER_APER_ENDIAN)) | SetBits(CTL_MEM_APER_BYTE_ENDIAN, CTL_MEM_LOWER_APER_ENDIAN); @@ -424,6 +425,7 @@ ATIMach64Save if (pATI->Chip >= ATI_CHIP_264VTB) { + pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE; pATIHW->mem_cntl = inr(MEM_CNTL); pATIHW->mpp_config = inr(MPP_CONFIG); pATIHW->mpp_strobe_seq = inr(MPP_STROBE_SEQ); @@ -1057,6 +1059,7 @@ ATIMach64Set if (pATI->Chip >= ATI_CHIP_264VTB) { + outr(MEM_BUF_CNTL, pATIHW->mem_buf_cntl); outr(MEM_CNTL, pATIHW->mem_cntl); outr(MPP_CONFIG, pATIHW->mpp_config); outr(MPP_STROBE_SEQ, pATIHW->mpp_strobe_seq); diff --git a/src/atimach64accel.c b/src/atimach64accel.c index 932c8c11..a0a9e176 100644 --- a/src/atimach64accel.c +++ b/src/atimach64accel.c @@ -245,16 +245,32 @@ ATIMach64Sync } } + if (pATI->pXAAInfo) + pATI->pXAAInfo->NeedToSync = FALSE; + + if (pATI->Chip >= ATI_CHIP_264VTB) + { + /* + * Flush the read-back cache (by turning on INVALIDATE_RB_CACHE), + * otherwise the host might get stale data when reading through the + * aperture. + */ + outr(MEM_BUF_CNTL, pATI->NewHW.mem_buf_cntl); + } + /* + * Note: + * Before actually invalidating the read-back cache, the mach64 driver + * was using the trick below which is buggy. The code is left here for + * reference, DRI uses this trick and needs updating. + * * For VTB's and later, the first CPU read of the framebuffer will return * zeroes, so do it here. This appears to be due to some kind of engine * caching of framebuffer data I haven't found any way of disabling, or * otherwise circumventing. Thanks to Mark Vojkovich for the suggestion. + * + * pATI = *(volatile ATIPtr *)pATI->pMemory; */ - if (pATI->pXAAInfo) - pATI->pXAAInfo->NeedToSync = FALSE; - - pATI = *(volatile ATIPtr *)pATI->pMemory; } static __inline__ void diff --git a/src/atiregs.h b/src/atiregs.h index f9730c71..102347b4 100644 --- a/src/atiregs.h +++ b/src/atiregs.h @@ -692,6 +692,19 @@ /* ? 0xf8000000ul */ #define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ #define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ +#define Z_WB_FLUSH 0x00000007ul +#define Z_WB_FLUSH_P 0x0000000ful /* GTPro */ +#define VID_WB_FLUSH_P 0x000000f0ul /* GTPro */ +#define VID_WB_FLUSH_MSB 0x00000100ul +#define GUI_WB_FLUSH_P 0x00001f00ul /* GTPro */ +#define HST_WB_FLUSH_P 0x0000e000ul /* GTPro */ +#define SCL_MIN_BURST_LEN 0x001f0000ul +#define SCL_THRESH 0x003f0000ul /* GTPro */ +/* ? 0x00400000ul */ +#define INVALIDATE_RB_CACHE 0x00800000ul +#define HST_WB_FLUSH 0x03000000ul +#define VID_WB_FLUSH 0x1c000000ul +#define GUI_WB_FLUSH 0xe0000000ul #define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ #define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ #define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ diff --git a/src/atistruct.h b/src/atistruct.h index 0aa37b5e..0201042e 100644 --- a/src/atistruct.h +++ b/src/atistruct.h @@ -110,7 +110,7 @@ typedef struct _ATIHWRec /* Mach64 CPIO registers */ CARD32 crtc_h_total_disp, crtc_h_sync_strt_wid, crtc_v_total_disp, crtc_v_sync_strt_wid, - crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, + crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, mem_buf_cntl, ovr_clr, ovr_wid_left_right, ovr_wid_top_bottom, cur_clr0, cur_clr1, cur_offset, cur_horz_vert_posn, cur_horz_vert_off, |