diff options
author | Eric Anholt <anholt@freebsd.org> | 2005-09-27 23:34:11 +0000 |
---|---|---|
committer | Eric Anholt <anholt@freebsd.org> | 2005-09-27 23:34:11 +0000 |
commit | bc3c26fe365347c427e04385c1df95a5eec14f28 (patch) | |
tree | 66e8b75f4d98a8aba25e024fd20391f88f8a901b /src | |
parent | 58dfb95c446b73fbc34784f0894cf89152dab043 (diff) |
Fix Radeon MMIO Render acceleration with EXA by writing out floating- point
coordinates rather than integers.
Diffstat (limited to 'src')
-rw-r--r-- | src/radeon_exa.c | 1 | ||||
-rw-r--r-- | src/radeon_exa_render.c | 13 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/radeon_exa.c b/src/radeon_exa.c index e5a9f210..9e962869 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -325,6 +325,7 @@ do { \ #define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) +#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) #define FINISH_ACCEL() #ifdef RENDER diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index d4beb874..3445e577 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -150,6 +150,7 @@ static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) return TRUE; } + static CARD32 RADEONGetBlendCntl(int op, CARD32 dst_format) { CARD32 blendcntl = RadeonBlendOp[op].blend_cntl; @@ -678,12 +679,12 @@ do { \ #define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _dstY); \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _srcX); \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _srcY); \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _maskX); \ - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, _maskY); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \ + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ } while (0) #endif /* !ACCEL_CP */ |