diff options
| author | Roland Mainz <roland.mainz@nrubsig.org> | 2004-12-17 00:13:18 +0000 |
|---|---|---|
| committer | Roland Mainz <roland.mainz@nrubsig.org> | 2004-12-17 00:13:18 +0000 |
| commit | 5b940ce78ec0221465c900b4b5a4fd8853ebbba4 (patch) | |
| tree | 16ff9be94794b3ed5eaffb78cb575de81b3b49ae /src | |
| parent | 5ffd2ba72362543c394c6349fc0c82c2bca450f1 (diff) | |
//bugs.freedesktop.org/show_bug.cgi?id=1220) attachment #980XORG-6_8_1_902XORG-6_8_1_901
(https://bugs.freedesktop.org/attachment.cgi?id=980): Fix garbage
screen on radeon cards which may appear after a system suspend/resume
cycle. Patch by Matthias Hopf <mhopf@suse.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/radeon_driver.c | 11 | ||||
| -rw-r--r-- | src/radeon_reg.h | 2 |
2 files changed, 8 insertions, 5 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 8bf3646a..b9a6a3a4 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -4495,10 +4495,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) RADEONSave(pScrn); - if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { - RADEONSetDynamicClock(pScrn, 1); - } else { - RADEONSetDynamicClock(pScrn, 0); + if ((!info->IsSecondary) && info->IsMobility) { + if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { + RADEONSetDynamicClock(pScrn, 1); + } else { + RADEONSetDynamicClock(pScrn, 0); + } } if (info->FBDev) { @@ -7157,6 +7159,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) RADEONDoAdjustFrame(pScrn, x, y, FALSE); } + RADEONSetFBLocation (pScrn); #ifdef XF86DRI if (info->CPStarted) DRIUnlock(pScrn->pScreen); #endif diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 8849cabd..b56630ce 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -803,7 +803,7 @@ # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12) # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) -# define RADEON_IO_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 |