R6xx/R7xx Xv: Add native support for packed formats

4 files changed, 35 insertions, 50 deletions

diff --git a/src/r600_exa.c b/src/r600_exa.c
index 598a5aca..6fd922cd 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2305,7 +2305,7 @@ R600LoadShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen)
     accel_state->comp_mask_vs_offset = 3072;
     accel_state->comp_mask_ps_offset = 3584;
     accel_state->xv_vs_offset = 4096;
-    accel_state->xv_ps_offset_nv12 = 4608;
+    accel_state->xv_ps_offset_packed = 4608;
     accel_state->xv_ps_offset_planar = 5120;
 
     // solid vs ---------------------------------------
@@ -2795,8 +2795,8 @@ R600LoadShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen)
 			 MEGA_FETCH(0));
     vs[i++] = VTX_DWORD_PAD;
 
-    // xv ps nv12 ----------------------------------
-    i = accel_state->xv_ps_offset_nv12 / 4;
+    // xv ps packed ----------------------------------
+    i = accel_state->xv_ps_offset_packed / 4;
     // 0
     ps[i++] = CF_DWORD0(ADDR(20));
     ps[i++] = CF_DWORD1(POP_COUNT(0),
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 82de88ae..993a8d4a 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -119,7 +119,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     case FOURCC_YUY2:
     default:
 	accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset +
-	    accel_state->xv_ps_offset_nv12;
+	    accel_state->xv_ps_offset_packed;
 	break;
     }
 
@@ -268,14 +268,17 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	tex_res.id                  = 0;
 	tex_res.w                   = pPriv->w;
 	tex_res.h                   = pPriv->h;
-	tex_res.pitch               = accel_state->src_pitch[0];
+	tex_res.pitch               = accel_state->src_pitch[0] >> 1;
 	tex_res.depth               = 0;
 	tex_res.dim                 = SQ_TEX_DIM_2D;
 	tex_res.base                = accel_state->src_mc_addr[0];
 	tex_res.mip_base            = accel_state->src_mc_addr[0];
 
-	tex_res.format              = FMT_8;
-	tex_res.dst_sel_x           = SQ_SEL_X; //Y
+	tex_res.format              = FMT_8_8;
+	if (pPriv->id == FOURCC_UYVY)
+	    tex_res.dst_sel_x           = SQ_SEL_Y; //Y
+	else
+	    tex_res.dst_sel_x           = SQ_SEL_X; //Y
 	tex_res.dst_sel_y           = SQ_SEL_1;
 	tex_res.dst_sel_z           = SQ_SEL_1;
 	tex_res.dst_sel_w           = SQ_SEL_1;
@@ -302,26 +305,24 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	set_tex_sampler             (pScrn, accel_state->ib, &tex_samp);
 
 	// UV texture
-	uv_offset = accel_state->src_pitch[0] * pPriv->h;
-	uv_offset = (uv_offset + 255) & ~255;
-
-	cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
-			    accel_state->src_size[0] / 2,
-			    accel_state->src_mc_addr[0] + uv_offset);
-
 	tex_res.id                  = 1;
-	tex_res.format              = FMT_8_8;
+	tex_res.format              = FMT_8_8_8_8;
 	tex_res.w                   = pPriv->w >> 1;
-	tex_res.h                   = pPriv->h >> 1;
-	tex_res.pitch               = accel_state->src_pitch[0] >> 1;
-	tex_res.dst_sel_x           = SQ_SEL_Y; //V
-	tex_res.dst_sel_y           = SQ_SEL_X; //U
+	tex_res.h                   = pPriv->h;
+	tex_res.pitch               = accel_state->src_pitch[0] >> 2;
+	if (pPriv->id == FOURCC_UYVY) {
+	    tex_res.dst_sel_x           = SQ_SEL_X; //V
+	    tex_res.dst_sel_y           = SQ_SEL_Z; //U
+	} else {
+	    tex_res.dst_sel_x           = SQ_SEL_Y; //V
+	    tex_res.dst_sel_y           = SQ_SEL_W; //U
+	}
 	tex_res.dst_sel_z           = SQ_SEL_1;
 	tex_res.dst_sel_w           = SQ_SEL_1;
 	tex_res.interlaced          = 0;
 	// XXX tex bases need to be 256B aligned
-	tex_res.base                = accel_state->src_mc_addr[0] + uv_offset;
-	tex_res.mip_base            = accel_state->src_mc_addr[0] + uv_offset;
+	tex_res.base                = accel_state->src_mc_addr[0];
+	tex_res.mip_base            = accel_state->src_mc_addr[0];
 	set_tex_resource            (pScrn, accel_state->ib, &tex_res);
 
 	// UV sampler
diff --git a/src/radeon.h b/src/radeon.h
index 2974cdf4..9b42afdd 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -658,7 +658,7 @@ struct radeon_accel_state {
     uint32_t          comp_mask_vs_offset;
     uint32_t          comp_mask_ps_offset;
     uint32_t          xv_vs_offset;
-    uint32_t          xv_ps_offset_nv12;
+    uint32_t          xv_ps_offset_packed;
     uint32_t          xv_ps_offset_planar;
 
     //size/addr stuff
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 6097ab56..eeaf9909 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -199,33 +199,17 @@ CopyPackedtoNV12(unsigned char *src, unsigned char *dst,
 		 int srcPitch, int dstPitch,
 		 int w, int h, int id)
 {
-    int i, j;
-    int uv_offset = dstPitch * h;
-    uv_offset = (uv_offset + 255) & ~255;
-
-    // FOURCC_UYVY: U0 Y0 V0 Y1
-    // FOURCC_YUY2: Y0 U0 Y1 V0
-    for (i = 0; i < h; i++) {
-	unsigned char *y = dst;
-	unsigned char *uv = (unsigned char *)dst + uv_offset;
-
-	for (j = 0; j < (w / 2); j++) {
-	    if (id == FOURCC_UYVY) {
-		uv[1] = src[(j * 4) + 0];
-		y[0]  = src[(j * 4) + 1];
-		uv[0] = src[(j * 4) + 2];
-		y[1]  = src[(j * 4) + 3];
-	    } else {
-		y[0]  = src[(j * 4) + 0];
-		uv[1] = src[(j * 4) + 1];
-		y[1]  = src[(j * 4) + 2];
-		uv[0] = src[(j * 4) + 3];
-	    }
-	    y += 2;
-	    uv += 2;
-	}
-	dst += dstPitch;
-	src += srcPitch;
+    int i;
+
+    if (srcPitch == dstPitch) {
+        memcpy(dst, src, srcPitch * h);
+	dst += (dstPitch * h);
+    } else {
+	for (i = 0; i < h; i++) {
+            memcpy(dst, src, srcPitch);
+            src += srcPitch;
+            dst += dstPitch;
+        }
     }
 }
 
@@ -298,7 +282,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
     }
 
     if (info->ChipFamily >= CHIP_FAMILY_R600)
-	dstPitch = (dstPitch + 511) & ~511;
+	dstPitch = (dstPitch + 255) & ~255;
     else
 	dstPitch = (dstPitch + 63) & ~63;