diff options
| author | Matt Turner <mattst88@gmail.com> | 2008-05-12 12:06:33 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.com> | 2008-05-12 12:06:33 -0400 |
| commit | 908b7b940e3ef296836bc94680ebb8ab67650e31 (patch) | |
| tree | 20edaba5bffdef2b3625f73ff5d297d3b0c952cb /src | |
| parent | 87e66ce76430890ab4939ffcd42f72b9288eb598 (diff) | |
Replace CARD{8,16,32} with uint{8,16,32}_t
As has been done with xf86-video-intel, replace all CARD* datatypes with
uint*_t datatypes available from stdint.h.
Diffstat (limited to 'src')
37 files changed, 1414 insertions, 1414 deletions
@@ -78,7 +78,7 @@ enum ATI_CHIP_FAMILY_Radeon }; -static int ATIChipID(const CARD16); +static int ATIChipID(const uint16_t); #ifdef XSERVER_LIBPCIACCESS @@ -249,7 +249,7 @@ ati_gdev_subdriver(pointer options) * This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID. */ static int -ATIChipID(const CARD16 ChipID) +ATIChipID(const uint16_t ChipID) { switch (ChipID) { diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index bab56b28..5cb79e27 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -168,8 +168,8 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); unsigned char *RADEONMMIO = info->MMIO; int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); - CARD32 sclock = mode->Clock; - CARD32 ref_div = 0, fb_div = 0, post_div = 0; + uint32_t sclock = mode->Clock; + uint32_t ref_div = 0, fb_div = 0, post_div = 0; int major, minor, i; SET_PIXEL_CLOCK_PS_ALLOCATION spc_param; PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; @@ -185,7 +185,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) RADEONSavePtr save = info->ModeReg; if (IS_AVIVO_VARIANT) { - CARD32 temp; + uint32_t temp; if (IS_DCE3_VARIANT) pll_flags |= RADEON_PLL_DCE3; @@ -407,7 +407,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); if (IS_AVIVO_VARIANT) { - CARD32 fb_format; + uint32_t fb_format; switch (crtc->scrn->bitsPerPixel) { case 15: diff --git a/src/generic_bus.h b/src/generic_bus.h index 6197eabd..ecefdcdb 100644 --- a/src/generic_bus.h +++ b/src/generic_bus.h @@ -21,10 +21,10 @@ typedef struct _GENERIC_BUS_Rec{ int scrnIndex; DevUnion DriverPrivate; Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *); - Bool (*read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); - Bool (*write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); - Bool (*fifo_read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); - Bool (*fifo_write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); + Bool (*read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); + Bool (*write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); + Bool (*fifo_read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); + Bool (*fifo_write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); } GENERIC_BUS_Rec; diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 5ef86ce4..c4e1650d 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -92,7 +92,7 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, if (pRADEONEnt->HasCRTC2 && info->ChipFamily != CHIP_FAMILY_R200 && !IS_R300_VARIANT) { - CARD32 tmp; + uint32_t tmp; tmp = INREG(RADEON_DAC_CNTL2); OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); @@ -155,7 +155,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - /* CARD32 crtc2_gen_cntl;*/ + /* uint32_t crtc2_gen_cntl;*/ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Programming CRTC2, offset: 0x%08x\n", @@ -239,9 +239,9 @@ RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); } -static CARD8 -RADEONComputePLLGain(CARD16 reference_freq, CARD16 ref_div, - CARD16 fb_div) +static uint8_t +RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, + uint16_t fb_div) { unsigned vcoFreq; @@ -278,7 +278,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD8 pllGain; + uint8_t pllGain; #if defined(__powerpc__) /* apparently restoring the pll causes a hang??? */ @@ -317,7 +317,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, RADEON_PPLL_RESET | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN - | ((CARD32)pllGain << RADEON_PPLL_PVG_SHIFT), + | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), ~(RADEON_PPLL_RESET | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN @@ -400,7 +400,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD8 pllGain; + uint8_t pllGain; pllGain = RADEONComputePLLGain(info->pll.reference_freq, restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, @@ -415,7 +415,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, RADEON_P2PLL_CNTL, RADEON_P2PLL_RESET | RADEON_P2PLL_ATOMIC_UPDATE_EN - | ((CARD32)pllGain << RADEON_P2PLL_PVG_SHIFT), + | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), ~(RADEON_P2PLL_RESET | RADEON_P2PLL_ATOMIC_UPDATE_EN | RADEON_P2PLL_PVG_MASK)); @@ -1145,10 +1145,10 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 feedback_div = 0; - CARD32 reference_div = 0; - CARD32 post_divider = 0; - CARD32 freq = 0; + uint32_t feedback_div = 0; + uint32_t reference_div = 0; + uint32_t post_divider = 0; + uint32_t freq = 0; struct { int divider; @@ -1226,10 +1226,10 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 feedback_div = 0; - CARD32 reference_div = 0; - CARD32 post_divider = 0; - CARD32 freq = 0; + uint32_t feedback_div = 0; + uint32_t reference_div = 0; + uint32_t post_divider = 0; + uint32_t freq = 0; struct { int divider; @@ -1308,16 +1308,16 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; + uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; float mem_tcas; int k1, c; - CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; - CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4}; - CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint32_t MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; + uint32_t MemTrpExtMemCntl[4] = {1, 2, 3, 4}; + uint32_t MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; + uint32_t MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint32_t MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint32_t MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; @@ -1340,7 +1340,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 * option. */ if ((info->DispPriority == 2) && IS_R300_VARIANT) { - CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); if (pRADEONEnt->pCrtc[1]->enabled) { mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ } else { @@ -1514,7 +1514,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 /* Find the critical point of the display buffer. */ - critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); + critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); /* ???? */ /* @@ -1605,7 +1605,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); - critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority + + critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + disp_latency) * disp_drain_rate2 + 0.5); if (info->DispPriority == 2) { diff --git a/src/legacy_output.c b/src/legacy_output.c index a65a41e0..962887aa 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c @@ -222,7 +222,7 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) } Bool -RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) +RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch) { if (!xf86I2CReadByte(dvo, addr, ch)) { xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, @@ -234,7 +234,7 @@ RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) } Bool -RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch) +RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch) { if (!xf86I2CWriteByte(dvo, addr, ch)) { xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, @@ -282,7 +282,7 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) OUTREG(radeon_output->dvo_i2c.mask_clk_reg, INREG(radeon_output->dvo_i2c.mask_clk_reg) & - (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); + (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); if (!RADEONInitExtTMDSInfoFromBIOS(output)) { if (radeon_output->DVOChip) { @@ -612,8 +612,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) unsigned char *RADEONMMIO = info->MMIO; if (IsPrimaryDAC) { - CARD32 dac_cntl; - CARD32 dac_macro_cntl = 0; + uint32_t dac_cntl; + uint32_t dac_macro_cntl = 0; dac_cntl = INREG(RADEON_DAC_CNTL); dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); if (IsOn) { @@ -630,8 +630,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) OUTREG(RADEON_DAC_CNTL, dac_cntl); OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); } else { - CARD32 tv_dac_cntl; - CARD32 fp2_gen_cntl; + uint32_t tv_dac_cntl; + uint32_t fp2_gen_cntl; switch(info->ChipFamily) { @@ -908,11 +908,11 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; int i; - CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; + uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; for (i=0; i<4; i++) { if (radeon_output->tmds_pll[i].freq == 0) break; - if ((CARD32)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { + if ((uint32_t)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { tmp = radeon_output->tmds_pll[i].value ; break; } @@ -1402,7 +1402,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, ErrorF("restore FP2\n"); if (info->IsAtomBios) { unsigned char *RADEONMMIO = info->MMIO; - CARD32 fp2_gen_cntl; + uint32_t fp2_gen_cntl; atombios_external_tmds_setup(output, mode); /* r4xx atom has hard coded crtc mappings in the atom code @@ -1446,8 +1446,8 @@ radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 vclk_ecp_cntl, crtc_ext_cntl; - CARD32 dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; + uint32_t vclk_ecp_cntl, crtc_ext_cntl; + uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; RADEONMonitorType found = MT_NONE; /* save the regs we need */ @@ -1513,11 +1513,11 @@ radeon_detect_ext_dac(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; - CARD32 disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; - CARD32 disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; - CARD32 tmp, crtc2_h_total_disp, crtc2_v_total_disp; - CARD32 crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; + uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; + uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; + uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; + uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; + uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; RADEONMonitorType found = MT_NONE; int connected = 0; int i = 0; @@ -1609,8 +1609,8 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; - CARD32 disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; + uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; + uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; RADEONMonitorType found = MT_NONE; /* save the regs we need */ @@ -1711,8 +1711,8 @@ r300_detect_tv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; - CARD32 gpiopad_a, disp_output_cntl; + uint32_t tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; + uint32_t gpiopad_a, disp_output_cntl; RADEONMonitorType found = MT_NONE; /* save the regs we need */ @@ -1787,8 +1787,8 @@ radeon_detect_tv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp, dac_cntl2, tv_master_cntl; - CARD32 tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; + uint32_t tmp, dac_cntl2, tv_master_cntl; + uint32_t tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; RADEONMonitorType found = MT_NONE; if (IS_R300_VARIANT) diff --git a/src/radeon.h b/src/radeon.h index feff48fc..187d3426 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -199,15 +199,15 @@ typedef enum { typedef struct { int revision; - CARD16 rr1_offset; - CARD16 rr2_offset; - CARD16 dyn_clk_offset; - CARD16 pll_offset; - CARD16 mem_config_offset; - CARD16 mem_reset_offset; - CARD16 short_mem_offset; - CARD16 rr3_offset; - CARD16 rr4_offset; + uint16_t rr1_offset; + uint16_t rr2_offset; + uint16_t dyn_clk_offset; + uint16_t pll_offset; + uint16_t mem_config_offset; + uint16_t mem_reset_offset; + uint16_t short_mem_offset; + uint16_t rr3_offset; + uint16_t rr4_offset; } RADEONBIOSInitTable; #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) @@ -217,21 +217,21 @@ typedef struct { #define RADEON_PLL_DCE3 (1 << 4) typedef struct { - CARD16 reference_freq; - CARD16 reference_div; - CARD32 pll_in_min; - CARD32 pll_in_max; - CARD32 pll_out_min; - CARD32 pll_out_max; - CARD16 xclk; - - CARD32 min_ref_div; - CARD32 max_ref_div; - CARD32 min_post_div; - CARD32 max_post_div; - CARD32 min_feedback_div; - CARD32 max_feedback_div; - CARD32 best_vco; + uint16_t reference_freq; + uint16_t reference_div; + uint32_t pll_in_min; + uint32_t pll_in_max; + uint32_t pll_out_min; + uint32_t pll_out_max; + uint16_t xclk; + + uint32_t min_ref_div; + uint32_t max_ref_div; + uint32_t min_post_div; + uint32_t max_post_div; + uint32_t min_feedback_div; + uint32_t max_feedback_div; + uint32_t best_vco; } RADEONPLLRec, *RADEONPLLPtr; typedef struct { @@ -357,7 +357,7 @@ typedef enum { typedef struct _atomBiosHandle *atomBiosHandlePtr; typedef struct { - CARD32 pci_device_id; + uint32_t pci_device_id; RADEONChipFamily chip_family; int mobility; int igp; @@ -377,22 +377,22 @@ typedef struct { unsigned long LinearAddr; /* Frame buffer physical address */ unsigned long MMIOAddr; /* MMIO region physical address */ unsigned long BIOSAddr; /* BIOS physical address */ - CARD32 fbLocation; - CARD32 gartLocation; - CARD32 mc_fb_location; - CARD32 mc_agp_location; - CARD32 mc_agp_location_hi; + uint32_t fbLocation; + uint32_t gartLocation; + uint32_t mc_fb_location; + uint32_t mc_agp_location; + uint32_t mc_agp_location_hi; void *MMIO; /* Map of MMIO region */ void *FB; /* Map of frame buffer */ - CARD8 *VBIOS; /* Video BIOS pointer */ + uint8_t *VBIOS; /* Video BIOS pointer */ Bool IsAtomBios; /* New BIOS used in R420 etc. */ int ROMHeaderStart; /* Start of the ROM Info Table */ int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ - CARD32 MemCntl; - CARD32 BusCntl; + uint32_t MemCntl; + uint32_t BusCntl; unsigned long MMIOSize; /* MMIO region physical address */ unsigned long FbMapSize; /* Size of frame buffer, in bytes */ unsigned long FbSecureSize; /* Size of secured fb area at end of @@ -472,9 +472,9 @@ typedef struct { /* Computed values for Radeon */ int pitch; int datatype; - CARD32 dp_gui_master_cntl; - CARD32 dp_gui_master_cntl_clip; - CARD32 trans_color; + uint32_t dp_gui_master_cntl; + uint32_t dp_gui_master_cntl_clip; + uint32_t trans_color; /* Saved values for ScreenToScreenCopy */ int xdir; @@ -500,7 +500,7 @@ typedef struct { #endif /* Saved values for DashedTwoPointLine */ int dashLen; - CARD32 dashPattern; + uint32_t dashPattern; int dash_fg; int dash_bg; @@ -511,7 +511,7 @@ typedef struct { DGAFunctionRec DGAFuncs; RADEONFBLayout CurrentLayout; - CARD32 dst_pitch_offset; + uint32_t dst_pitch_offset; #ifdef XF86DRI Bool noBackBuffer; Bool directRenderingEnabled; @@ -526,14 +526,14 @@ typedef struct { RADEONConfigPrivPtr pVisualConfigsPriv; Bool (*DRICloseScreen)(int, ScreenPtr); - drm_handle_t fbHandle; + drm_handle_t fbHandle; drmSize registerSize; - drm_handle_t registerHandle; + drm_handle_t registerHandle; RADEONCardType cardType; /* Current card is a PCI card */ drmSize pciSize; - drm_handle_t pciMemHandle; + drm_handle_t pciMemHandle; unsigned char *PCI; /* Map */ Bool depthMoves; /* Enable depth moves -- slow! */ @@ -546,12 +546,12 @@ typedef struct { int pciAperSize; drmSize gartSize; - drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ + drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ unsigned long gartOffset; unsigned char *AGP; /* Map */ int agpMode; - CARD32 pciCommand; + uint32_t pciCommand; Bool CPRuns; /* CP is running */ Bool CPInUse; /* CP has been used by X server */ @@ -563,20 +563,20 @@ typedef struct { /* CP ring buffer data */ unsigned long ringStart; /* Offset into GART space */ - drm_handle_t ringHandle; /* Handle from drmAddMap */ + drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ int ringSize; /* Size of ring (in MB) */ drmAddress ring; /* Map */ int ringSizeLog2QW; unsigned long ringReadOffset; /* Offset into GART space */ - drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ + drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ drmSize ringReadMapSize; /* Size of map */ drmAddress ringReadPtr; /* Map */ /* CP vertex/indirect buffer data */ unsigned long bufStart; /* Offset into GART space */ - drm_handle_t bufHandle; /* Handle from drmAddMap */ + drm_handle_t bufHandle; /* Handle from drmAddMap */ drmSize bufMapSize; /* Size of map */ int bufSize; /* Size of buffers (in MB) */ drmAddress buf; /* Map */ @@ -585,7 +585,7 @@ typedef struct { /* CP GART Texture data */ unsigned long gartTexStart; /* Offset into GART space */ - drm_handle_t gartTexHandle; /* Handle from drmAddMap */ + drm_handle_t gartTexHandle; /* Handle from drmAddMap */ drmSize gartTexMapSize; /* Size of map */ int gartTexSize; /* Size of GART tex space (in MB) */ drmAddress gartTex; /* Map */ @@ -615,12 +615,12 @@ typedef struct { int log2TexGran; int pciGartSize; - CARD32 pciGartOffset; + uint32_t pciGartOffset; void *pciGartBackup; #ifdef USE_XAA - CARD32 frontPitchOffset; - CARD32 backPitchOffset; - CARD32 depthPitchOffset; + uint32_t frontPitchOffset; + uint32_t backPitchOffset; + uint32_t depthPitchOffset; /* offscreen memory management */ int backLines; @@ -630,15 +630,15 @@ typedef struct { #endif /* Saved scissor values */ - CARD32 sc_left; - CARD32 sc_right; - CARD32 sc_top; - CARD32 sc_bottom; + uint32_t sc_left; + uint32_t sc_right; + uint32_t sc_top; + uint32_t sc_bottom; - CARD32 re_top_left; - CARD32 re_width_height; + uint32_t re_top_left; + uint32_t re_width_height; - CARD32 aux_sc_cntl; + uint32_t aux_sc_cntl; int irq; @@ -663,22 +663,22 @@ typedef struct { int RageTheatreCompositePort; int RageTheatreSVideoPort; int tunerType; - char* RageTheatreMicrocPath; - char* RageTheatreMicrocType; - Bool MM_TABLE_valid; + char* RageTheatreMicrocPath; + char* RageTheatreMicrocType; + Bool MM_TABLE_valid; struct { - CARD8 table_revision; - CARD8 table_size; - CARD8 tuner_type; - CARD8 audio_chip; - CARD8 product_id; - CARD8 tuner_voltage_teletext_fm; - CARD8 i2s_config; /* configuration of the sound chip */ - CARD8 video_decoder_type; - CARD8 video_decoder_host_config; - CARD8 input[5]; - } MM_TABLE; - CARD16 video_decoder_type; + uint8_t table_revision; + uint8_t table_size; + uint8_t tuner_type; + uint8_t audio_chip; + uint8_t product_id; + uint8_t tuner_voltage_teletext_fm; + uint8_t i2s_config; /* configuration of the sound chip */ + uint8_t video_decoder_type; + uint8_t video_decoder_host_config; + uint8_t input[5]; + } MM_TABLE; + uint16_t video_decoder_type; int overlay_scaler_buffer_width; int ecp_div; @@ -710,15 +710,15 @@ typedef struct { DisplayModePtr currentMode, savedCurrentMode; /* special handlings for DELL triple-head server */ - Bool IsDellServer; + Bool IsDellServer; - Bool VGAAccess; + Bool VGAAccess; - int MaxSurfaceWidth; - int MaxLines; + int MaxSurfaceWidth; + int MaxLines; - CARD32 tv_dac_adj; - CARD32 tv_dac_enable_mask; + uint32_t tv_dac_adj; + uint32_t tv_dac_enable_mask; Bool want_vblank_interrupts; RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; @@ -800,8 +800,8 @@ extern void legacy_output_dpms(xf86OutputPtr output, int mode); extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); -extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch); -extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch); +extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); +extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); @@ -816,20 +816,20 @@ extern void RADEONEngineFlush(ScrnInfoPtr pScrn); extern void RADEONEngineInit(ScrnInfoPtr pScrn); extern void RADEONEngineReset(ScrnInfoPtr pScrn); extern void RADEONEngineRestore(ScrnInfoPtr pScrn); -extern CARD8 *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, - unsigned int w, CARD32 dstPitchOff, - CARD32 *bufPitch, int x, int *y, +extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, + unsigned int w, uint32_t dstPitchOff, + uint32_t *bufPitch, int x, int *y, unsigned int *h, unsigned int *hpass); extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, unsigned int bpp, - CARD8 *dst, CARD8 *src, + uint8_t *dst, uint8_t *src, unsigned int hpass, unsigned int dstPitch, unsigned int srcPitch); -extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap); -extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, - CARD32 pitch, int cpp, - CARD32 *dstPitchOffset, int *x, int *y); +extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); +extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, + uint32_t pitch, int cpp, + uint32_t *dstPitchOffset, int *x, int *y); extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); #ifdef XF86DRI @@ -873,10 +873,10 @@ extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); extern void RADEONBlank(ScrnInfoPtr pScrn); extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, - CARD32 *chosen_dot_clock_freq, - CARD32 *chosen_feedback_div, - CARD32 *chosen_reference_div, - CARD32 *chosen_post_div, int flags); + uint32_t *chosen_dot_clock_freq, + uint32_t *chosen_feedback_div, + uint32_t *chosen_reference_div, + uint32_t *chosen_post_div, int flags); extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode); extern void RADEONUnblank(ScrnInfoPtr pScrn); @@ -885,7 +885,7 @@ extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); /* radeon_cursor.c */ extern Bool RADEONCursorInit(ScreenPtr pScreen); extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); -extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); +extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, uint32_t *image); extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); @@ -915,8 +915,8 @@ extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); extern int RADEONMinBits(int val); extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); -extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data); -extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); +extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); +extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); extern void RADEONPllErrataAfterData(RADEONInfoPtr info); extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); @@ -938,22 +938,22 @@ extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, extern Bool RADEONDrawInitCP(ScreenPtr pScreen); extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, - CARD32 src_pitch_offset, - CARD32 dst_pitch_offset, - CARD32 datatype, int rop, + uint32_t src_pitch_offset, + uint32_t dst_pitch_offset, + uint32_t datatype, int rop, Pixel planemask); extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, - CARD32 src_pitch_offset, - CARD32 dst_pitch_offset, - CARD32 datatype, int rop, + uint32_t src_pitch_offset, + uint32_t dst_pitch_offset, + uint32_t datatype, int rop, Pixel planemask); #endif #if defined(XF86DRI) && defined(USE_EXA) /* radeon_exa.c */ -extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type); +extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, - CARD32 *pitch_offset); + uint32_t *pitch_offset); extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); #endif @@ -1081,7 +1081,7 @@ do { \ #define RADEON_VERBOSE 0 -#define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0 +#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ if (RADEON_VERBOSE) { \ @@ -1099,7 +1099,7 @@ do { \ if (!info->indirectBuffer) { \ info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ info->indirectStart = 0; \ - } else if (info->indirectBuffer->used + (n) * (int)sizeof(CARD32) > \ + } else if (info->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ info->indirectBuffer->total) { \ RADEONCPFlushIndirect(pScrn, 1); \ } \ @@ -1126,9 +1126,9 @@ do { \ "ADVANCE_RING() start: %d used: %d count: %d\n", \ info->indirectStart, \ info->indirectBuffer->used, \ - __count * (int)sizeof(CARD32)); \ + __count * (int)sizeof(uint32_t)); \ } \ - info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ + info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ } while (0) #define OUT_RING(x) do { \ diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 9e7ea7a5..d2851a7a 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -192,10 +192,10 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 clock_cntl_index; - CARD32 mclk_cntl; - CARD32 rbbm_soft_reset; - CARD32 host_path_cntl; + uint32_t clock_cntl_index; + uint32_t mclk_cntl; + uint32_t rbbm_soft_reset; + uint32_t host_path_cntl; /* The following RBBM_SOFT_RESET sequence can help un-wedge * an R300 after the command processor got stuck. @@ -210,7 +210,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_RB)); INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | @@ -232,7 +232,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) * ASIC-version dependent, so we force all blocks on for now */ if (info->HasCRTC2) { - CARD32 tmp; + uint32_t tmp; tmp = INPLL(pScrn, RADEON_SCLK_CNTL); OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) | @@ -266,7 +266,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - CARD32 tmp; + uint32_t tmp; OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_SOFT_RESET_CP | @@ -285,7 +285,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_RB)); INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | @@ -398,7 +398,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) } if (IS_R300_3D | IS_R500_3D) { - CARD32 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); + uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); switch(info->num_gb_pipes) { case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; @@ -681,11 +681,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) * about tiling etc. */ void -RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, - CARD32 *dstPitchOff, int *x, int *y) +RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, uint32_t pitch, int cpp, + uint32_t *dstPitchOff, int *x, int *y) { RADEONInfoPtr info = RADEONPTR( pScrn ); - CARD32 dstOffs = dst - (CARD8*)info->FB + info->fbLocation; + uint32_t dstOffs = dst - (uint8_t*)info->FB + info->fbLocation; *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; @@ -696,21 +696,21 @@ RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, * framebuffer. Returns the address where the data can be written to and sets * the dstPitch and hpass variables as required. */ -CARD8* +uint8_t* RADEONHostDataBlit( ScrnInfoPtr pScrn, unsigned int cpp, unsigned int w, - CARD32 dstPitchOff, - CARD32 *bufPitch, + uint32_t dstPitchOff, + uint32_t *bufPitch, int x, int *y, unsigned int *h, unsigned int *hpass ){ RADEONInfoPtr info = RADEONPTR( pScrn ); - CARD32 format, dwords; - CARD8 *ret; + uint32_t format, dwords; + uint8_t *ret; RING_LOCALS; if ( *h == 0 ) @@ -783,7 +783,7 @@ RADEONHostDataBlit( OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); OUT_RING( dwords ); - ret = ( CARD8* )&__head[__count]; + ret = ( uint8_t* )&__head[__count]; __count += dwords; ADVANCE_RING(); @@ -794,7 +794,7 @@ RADEONHostDataBlit( return ret; } -void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap) +void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) { switch(swap) { case RADEON_HOST_DATA_SWAP_HDW: @@ -849,8 +849,8 @@ void RADEONHostDataBlitCopyPass( ScrnInfoPtr pScrn, unsigned int cpp, - CARD8 *dst, - CARD8 *src, + uint8_t *dst, + uint8_t *src, unsigned int hpass, unsigned int dstPitch, unsigned int srcPitch @@ -1139,7 +1139,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) /* Reserve space for textures */ info->textureOffset = ((info->FbMapSize - info->textureSize + RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); + ~(uint32_t)RADEON_BUFFER_ALIGN); } /* Reserve space for the shared depth @@ -1147,7 +1147,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) */ info->depthOffset = ((info->textureOffset - depthSize + RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); + ~(uint32_t)RADEON_BUFFER_ALIGN); /* Reserve space for the shared back buffer */ if (info->noBackBuffer) { @@ -1155,7 +1155,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) } else { info->backOffset = ((info->depthOffset - bufferSize + RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); + ~(uint32_t)RADEON_BUFFER_ALIGN); } info->backY = info->backOffset / width_bytes; diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c index bda15ffc..3c0b8a0f 100644 --- a/src/radeon_accelfuncs.c +++ b/src/radeon_accelfuncs.c @@ -284,7 +284,7 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, unsigned char *pattern) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 pat = *(CARD32 *)(pointer)pattern; + uint32_t pat = *(uint32_t *)(pointer)pattern; ACCEL_PREAMBLE(); /* Save for determining whether or not to draw last pixel */ @@ -333,7 +333,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, int fg) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 dp_gui_master_cntl = info->dp_gui_master_cntl_clip; + uint32_t dp_gui_master_cntl = info->dp_gui_master_cntl_clip; ACCEL_PREAMBLE(); dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK; @@ -548,8 +548,8 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx); OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny); #else - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(CARD32 *)(pointer)&pattern[0]); - OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(CARD32 *)(pointer)&pattern[4]); + OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(uint32_t *)(pointer)&pattern[0]); + OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(uint32_t *)(pointer)&pattern[4]); #endif FINISH_ACCEL(); @@ -829,10 +829,10 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef ACCEL_MMIO - CARD32 *p = (pointer)info->scratch_buffer[bufno]; + uint32_t *p = (pointer)info->scratch_buffer[bufno]; int i; int left = info->scanline_words; - volatile CARD32 *d; + volatile uint32_t *d; ACCEL_PREAMBLE(); if (info->scanline_direct) return; diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index b17b53c9..3c87f984 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -277,8 +277,8 @@ rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, Bool rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, - CARD8 *contentRev, - CARD8 *formatRev, + uint8_t *contentRev, + uint8_t *formatRev, unsigned short *size) { if (!hdr) @@ -456,7 +456,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, } if (fb_base && fb_size && size) { /* 4k align */ - fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0); + fb_size = (fb_size & ~(uint32_t)0xfff) + ((fb_size & 0xfff) ? 1 : 0); if ((fb_base + fb_size) > (start + size)) { xf86DrvMsg(handle->scrnIndex, X_WARNING, "%s: FW FB scratch area %i (size: %i)" @@ -687,7 +687,7 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD32 *val = &data->val; + uint32_t *val = &data->val; //RHDFUNC(handle); atomDataPtr = handle->atomDataPtr; @@ -712,7 +712,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD32 *val = &data->val; + uint32_t *val = &data->val; int idx = *val; atomDataPtr = handle->atomDataPtr; @@ -807,7 +807,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) } static unsigned char* -rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record) +rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record) { unsigned char *EDIDBlock; @@ -877,7 +877,7 @@ rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; + uint8_t crev, frev; DisplayModePtr last = NULL; DisplayModePtr new = NULL; DisplayModePtr first = NULL; @@ -967,7 +967,7 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; + uint8_t crev, frev; unsigned long offset; //RHDFUNC(handle); @@ -1031,8 +1031,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; - CARD32 *val = &data->val; + uint8_t crev, frev; + uint32_t *val = &data->val; //RHDFUNC(handle); @@ -1141,8 +1141,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; - CARD32 *val = &data->val; + uint8_t crev, frev; + uint32_t *val = &data->val; //RHDFUNC(handle); @@ -1198,8 +1198,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; - CARD32 *val = &data->val; + uint8_t crev, frev; + uint32_t *val = &data->val; unsigned short size; //RHDFUNC(handle); @@ -1238,8 +1238,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; - CARD32 *val = &data->val; + uint8_t crev, frev; + uint32_t *val = &data->val; //RHDFUNC(handle); @@ -1463,13 +1463,13 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle, } static RADEONI2CBusRec -RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) +RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) { RADEONInfoPtr info = RADEONPTR (pScrn); atomDataTablesPtr atomDataPtr; ATOM_GPIO_I2C_ASSIGMENT gpio; RADEONI2CBusRec i2c; - CARD8 crev, frev; + uint8_t crev, frev; memset(&i2c, 0, sizeof(RADEONI2CBusRec)); i2c.valid = FALSE; @@ -1524,7 +1524,7 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); - CARD8 crev, frev; + uint8_t crev, frev; unsigned short size; atomDataTablesPtr atomDataPtr; ATOM_CONNECTOR_OBJECT_TABLE *con_obj; @@ -1545,7 +1545,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) for (i = 0; i < con_obj->ucNumberOfObjects; i++) { ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; ATOM_COMMON_RECORD_HEADER *Record; - CARD8 obj_id, num, obj_type; + uint8_t obj_id, num, obj_type; int record_base; obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; @@ -1562,7 +1562,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if ((info->ChipFamily == CHIP_FAMILY_RS780) && (obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { - CARD32 slot_config, ct; + uint32_t slot_config, ct; igp_obj = info->atomBIOS->atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2; @@ -1588,7 +1588,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) info->BiosConnector[i].devices = 0; for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { - CARD8 sobj_id; + uint8_t sobj_id; sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id); @@ -1797,7 +1797,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); atomDataTablesPtr atomDataPtr; - CARD8 crev, frev; + uint8_t crev, frev; int i, j; atomDataPtr = info->atomBIOS->atomDataPtr; @@ -1964,9 +1964,9 @@ rhdAtomExec (atomBiosHandlePtr handle, __func__); return ATOM_FAILED; } - *dataSpace = (CARD8*)info->FB + handle->fbBase; + *dataSpace = (uint8_t*)info->FB + handle->fbBase; } else - *dataSpace = (CARD8*)handle->scratchBase; + *dataSpace = (uint8_t*)handle->scratchBase; } ret = ParseTableWrapper(pspace, idx, handle, handle->BIOSBase, @@ -2110,11 +2110,11 @@ CailReadFBData(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); if (((atomBiosHandlePtr)CAIL)->fbBase) { - CARD8 *FBBase = (CARD8*)info->FB; - ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); + uint8_t *FBBase = (uint8_t*)info->FB; + ret = *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { - ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); + ret = *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ } else { xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, @@ -2131,11 +2131,11 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));*/ if (((atomBiosHandlePtr)CAIL)->fbBase) { - CARD8 *FBBase = (CARD8*) + uint8_t *FBBase = (uint8_t*) RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB; - *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; + *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { - *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; + *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; } else xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); @@ -2191,13 +2191,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) switch (size) { case 8: - *(CARD8*)ret = pciReadByte(tag,idx << 2); + *(uint8_t*)ret = pciReadByte(tag,idx << 2); break; case 16: - *(CARD16*)ret = pciReadWord(tag,idx << 2); + *(uint16_t*)ret = pciReadWord(tag,idx << 2); break; case 32: - *(CARD32*)ret = pciReadLong(tag,idx << 2); + *(uint32_t*)ret = pciReadLong(tag,idx << 2); break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, @@ -2219,13 +2219,13 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));*/ switch (size) { case 8: - pciWriteByte(tag,idx << 2,*(CARD8*)src); + pciWriteByte(tag,idx << 2,*(uint8_t*)src); break; case 16: - pciWriteWord(tag,idx << 2,*(CARD16*)src); + pciWriteWord(tag,idx << 2,*(uint16_t*)src); break; case 32: - pciWriteLong(tag,idx << 2,*(CARD32*)src); + pciWriteLong(tag,idx << 2,*(uint32_t*)src); break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h index 955f2e4e..b4a19aad 100644 --- a/src/radeon_atombios.h +++ b/src/radeon_atombios.h @@ -98,7 +98,7 @@ typedef struct AtomFb { typedef union AtomBiosArg { - CARD32 val; + uint32_t val; struct rhdConnectorInfo *connectorInfo; unsigned char* EDIDBlock; atomBiosHandlePtr atomhandle; @@ -242,7 +242,7 @@ typedef struct _atomBiosHandle { atomDataTablesPtr atomDataPtr; unsigned int cmd_offset; pointer *scratchBase; - CARD32 fbBase; + uint32_t fbBase; #if XSERVER_LIBPCIACCESS struct pci_device *device; #else diff --git a/src/radeon_bios.c b/src/radeon_bios.c index 6be3528c..a3efe29c 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -570,7 +570,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); RADEONPLLPtr pll = &info->pll; - CARD16 pll_info_block; + uint16_t pll_info_block; if (!info->VBIOS) { return FALSE; @@ -847,16 +847,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) memcpy(EDID, (char*)(info->VBIOS + tmp), 256); - radeon_output->DotClock = (*(CARD16*)(EDID+54)) * 10; - radeon_output->PanelXRes = (*(CARD8*)(EDID+56)) + ((*(CARD8*)(EDID+58))>>4)*256; - radeon_output->HBlank = (*(CARD8*)(EDID+57)) + ((*(CARD8*)(EDID+58)) & 0xf)*256; - radeon_output->HOverPlus = (*(CARD8*)(EDID+62)) + ((*(CARD8*)(EDID+65)>>6)*256); - radeon_output->HSyncWidth = (*(CARD8*)(EDID+63)) + (((*(CARD8*)(EDID+65)>>4) & 3)*256); - radeon_output->PanelYRes = (*(CARD8*)(EDID+59)) + ((*(CARD8*)(EDID+61))>>4)*256; - radeon_output->VBlank = ((*(CARD8*)(EDID+60)) + ((*(CARD8*)(EDID+61)) & 0xf)*256); - radeon_output->VOverPlus = (((*(CARD8*)(EDID+64))>>4) + (((*(CARD8*)(EDID+65)>>2) & 3)*16)); - radeon_output->VSyncWidth = (((*(CARD8*)(EDID+64)) & 0xf) + ((*(CARD8*)(EDID+65)) & 3)*256); - radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(CARD8*)(EDID+71);*/ + radeon_output->DotClock = (*(uint16_t*)(EDID+54)) * 10; + radeon_output->PanelXRes = (*(uint8_t*)(EDID+56)) + ((*(uint8_t*)(EDID+58))>>4)*256; + radeon_output->HBlank = (*(uint8_t*)(EDID+57)) + ((*(uint8_t*)(EDID+58)) & 0xf)*256; + radeon_output->HOverPlus = (*(uint8_t*)(EDID+62)) + ((*(uint8_t*)(EDID+65)>>6)*256); + radeon_output->HSyncWidth = (*(uint8_t*)(EDID+63)) + (((*(uint8_t*)(EDID+65)>>4) & 3)*256); + radeon_output->PanelYRes = (*(uint8_t*)(EDID+59)) + ((*(uint8_t*)(EDID+61))>>4)*256; + radeon_output->VBlank = ((*(uint8_t*)(EDID+60)) + ((*(uint8_t*)(EDID+61)) & 0xf)*256); + radeon_output->VOverPlus = (((*(uint8_t*)(EDID+64))>>4) + (((*(uint8_t*)(EDID+65)>>2) & 3)*16)); + radeon_output->VSyncWidth = (((*(uint8_t*)(EDID+64)) & 0xf) + ((*(uint8_t*)(EDID+65)) & 3)*256); + radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(uint8_t*)(EDID+71);*/ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); } return TRUE; @@ -867,7 +867,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; - CARD32 tmp, maxfreq; + uint32_t tmp, maxfreq; int i, n; if (!info->VBIOS) return FALSE; @@ -988,7 +988,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) unsigned char *RADEONMMIO = info->MMIO; RADEONOutputPrivatePtr radeon_output = output->driver_private; int offset, index, id; - CARD32 val, reg, andmask, ormask; + uint32_t val, reg, andmask, ormask; if (!info->VBIOS) return FALSE; @@ -1098,11 +1098,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) #define RADEON_PLL_WAIT_DLL_READY_MASK 4 #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 -static CARD16 -RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, CARD16 offset) +static uint16_t +RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) { RADEONInfoPtr info = RADEONPTR (pScrn); - CARD8 revision = RADEON_BIOS8(offset - 1); + uint8_t revision = RADEON_BIOS8(offset - 1); if (revision > 0x10) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, @@ -1123,7 +1123,7 @@ Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); - CARD8 val; + uint8_t val; if (!info->VBIOS) { return FALSE; @@ -1217,14 +1217,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) } static void -RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) { RADEONInfoPtr info = RADEONPTR (pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD16 offset = table_offset; - CARD16 value, flag, index, count; - CARD32 andmask, ormask, val, channel_complete_mask; - CARD8 command; + uint16_t offset = table_offset; + uint16_t value, flag, index, count; + uint32_t andmask, ormask, val, channel_complete_mask; + uint8_t command; if (offset == 0) return; @@ -1325,14 +1325,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void -RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) { RADEONInfoPtr info = RADEONPTR (pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD16 offset = table_offset; - CARD16 count; - CARD32 ormask, val, channel_complete_mask; - CARD8 index; + uint16_t offset = table_offset; + uint16_t count; + uint32_t ormask, val, channel_complete_mask; + uint8_t index; if (offset == 0) return; @@ -1369,7 +1369,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) val = (val & RADEON_SDRAM_MODE_MASK) | ormask; OUTREG(RADEON_MM_DATA, val); - ormask = (CARD32)index << 24; + ormask = (uint32_t)index << 24; ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", RADEON_B3MEM_RESET_MASK, (unsigned)ormask); @@ -1384,13 +1384,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void -RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) { RADEONInfoPtr info = RADEONPTR (pScrn); - CARD16 offset = table_offset; - CARD8 index, shift; - CARD32 andmask, ormask, val, clk_pwrmgt_cntl; - CARD16 count; + uint16_t offset = table_offset; + uint8_t index, shift; + uint32_t andmask, ormask, val, clk_pwrmgt_cntl; + uint16_t count; if (offset == 0) return; @@ -1452,11 +1452,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) offset++; andmask = - (((CARD32)RADEON_BIOS8(offset)) << shift) | - ~((CARD32)0xff << shift); + (((uint32_t)RADEON_BIOS8(offset)) << shift) | + ~((uint32_t)0xff << shift); offset++; - ormask = ((CARD32)RADEON_BIOS8(offset)) << shift; + ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; offset++; ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index 9a450f94..631c3509 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -55,7 +55,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 gb_tile_config, su_reg_dest, vap_cntl; + uint32_t gb_tile_config, su_reg_dest, vap_cntl; ACCEL_PREAMBLE(); info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 6a9a76d0..b1e978c0 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -113,7 +113,7 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc) radeon_crtc_dpms(crtc, DPMSModeOff); } -static CARD32 RADEONDiv(CARD64 n, CARD32 d) +static uint32_t RADEONDiv(CARD64 n, uint32_t d) { return (n + (d / 2)) / d; } @@ -121,22 +121,22 @@ static CARD32 RADEONDiv(CARD64 n, CARD32 d) void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, - CARD32 *chosen_dot_clock_freq, - CARD32 *chosen_feedback_div, - CARD32 *chosen_reference_div, - CARD32 *chosen_post_div, + uint32_t *chosen_dot_clock_freq, + uint32_t *chosen_feedback_div, + uint32_t *chosen_reference_div, + uint32_t *chosen_post_div, int flags) { - CARD32 min_ref_div = pll->min_ref_div; - CARD32 max_ref_div = pll->max_ref_div; - CARD32 best_vco = pll->best_vco; - CARD32 best_post_div = 1; - CARD32 best_ref_div = 1; - CARD32 best_feedback_div = 1; - CARD32 best_freq = 1; - CARD32 best_error = 0xffffffff; - CARD32 best_vco_diff = 1; - CARD32 post_div; + uint32_t min_ref_div = pll->min_ref_div; + uint32_t max_ref_div = pll->max_ref_div; + uint32_t best_vco = pll->best_vco; + uint32_t best_post_div = 1; + uint32_t best_ref_div = 1; + uint32_t best_feedback_div = 1; + uint32_t best_freq = 1; + uint32_t best_error = 0xffffffff; + uint32_t best_vco_diff = 1; + uint32_t post_div; freq = freq * 1000; @@ -146,8 +146,8 @@ RADEONComputePLL(RADEONPLLPtr pll, min_ref_div = max_ref_div = pll->reference_div; for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { - CARD32 ref_div; - CARD32 vco = (freq / 10000) * post_div; + uint32_t ref_div; + uint32_t vco = (freq / 10000) * post_div; if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) continue; @@ -166,8 +166,8 @@ RADEONComputePLL(RADEONPLLPtr pll, continue; for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { - CARD32 feedback_div, current_freq, error, vco_diff; - CARD32 pll_in = pll->reference_freq / ref_div; + uint32_t feedback_div, current_freq, error, vco_diff; + uint32_t pll_in = pll->reference_freq / ref_div; if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) continue; @@ -296,8 +296,8 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) static void -radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, - CARD16 *blue, int size) +radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, + uint16_t *blue, int size) { RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ScrnInfoPtr pScrn = crtc->scrn; diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index d68d64b0..3ca576b5 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -115,7 +115,7 @@ avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock) RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(crtc->scrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; + uint32_t tmp; tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); @@ -255,8 +255,8 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) { ScrnInfoPtr pScrn = crtc->scrn; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset); + RADEONInfoPtr info = RADEONPTR(pScrn); + uint32_t *pixels = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); int pixel, i; CURSOR_SWAPPING_DECL_MMIO @@ -293,13 +293,13 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) #ifdef ARGB_CURSOR void -radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) +radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, uint32_t *image) { ScrnInfoPtr pScrn = crtc->scrn; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); CURSOR_SWAPPING_DECL_MMIO - CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset); + uint32_t *d = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); RADEONCTRACE(("RADEONLoadCursorARGB\n")); @@ -325,13 +325,13 @@ Bool RADEONCursorInit(ScreenPtr pScreen) int width_bytes; int height; int size_bytes; - CARD32 cursor_offset = 0; + uint32_t cursor_offset = 0; int c; - size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; - width = pScrn->displayWidth; - width_bytes = width * (pScrn->bitsPerPixel / 8); - height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; + size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; + width = pScrn->displayWidth; + width_bytes = width * (pScrn->bitsPerPixel / 8); + height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; #ifdef USE_XAA if (!info->useEXA) { diff --git a/src/radeon_dga.c b/src/radeon_dga.c index ab5d278d..d623fe43 100644 --- a/src/radeon_dga.c +++ b/src/radeon_dga.c @@ -374,7 +374,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, /* XXX */ if (info->useEXA) { /* - info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (CARD32)(~0)); + info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (uint32_t)(~0)); info->exa.accel.Solid(pScrn, x, y, x+w, y+h); info->exa.accel.DoneSolid(); */ @@ -383,7 +383,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, #endif /* USE_EXA */ #ifdef USE_XAA if (!info->useEXA) { - (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (CARD32)(~0)); + (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (uint32_t)(~0)); (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h); if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) RADEON_MARK_SYNC(info, pScrn); @@ -404,7 +404,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, /* XXX */ if (info->useEXA) { /* - info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (CARD32)(~0)); + info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (uint32_t)(~0)); info->exa.accel.Copy(pScrn, srcx, srcy, dstx, dsty, w, h); info->exa.accel.DoneCopy(); */ @@ -414,7 +414,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, #ifdef USE_XAA if (!info->useEXA) { (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, - GXcopy, (CARD32)(~0), -1); + GXcopy, (uint32_t)(~0), -1); (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy, dstx, dsty, w, h); if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) @@ -433,7 +433,7 @@ static void RADEON_BlitTransRect(ScrnInfoPtr pScrn, info->XAAForceTransBlit = TRUE; (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, - GXcopy, (CARD32)(~0), color); + GXcopy, (uint32_t)(~0), color); info->XAAForceTransBlit = FALSE; diff --git a/src/radeon_dri.c b/src/radeon_dri.c index ac8d03c9..f7f3e40e 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType, /* 16-bit depth buffer functions */ #define WRITE_DEPTH16(_x, _y, d) \ - *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) + *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) #define READ_DEPTH16(d, _x, _y) \ - (d) = *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) + (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) /* 32-bit depth buffer (stencil and depth simultaneously) functions */ #define WRITE_DEPTHSTENCIL32(_x, _y, d) \ - *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) + *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) #define READ_DEPTHSTENCIL32(d, _x, _y) \ - (d) = *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) + (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) /* Screen to screen copy of data in the depth buffer */ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, @@ -508,7 +508,7 @@ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, #endif /* USE_XAA */ /* Initialize the state of the back and depth buffers */ -static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx) +static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, uint32_t indx) { /* NOOP. There's no need for the 2d driver to be clearing buffers * for the 3d client. It knows how to do that on its own. @@ -523,7 +523,7 @@ static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx) * are reversed. */ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, - RegionPtr prgnSrc, CARD32 indx) + RegionPtr prgnSrc, uint32_t indx) { #ifdef USE_XAA ScreenPtr pScreen = pParent->drawable.pScreen; @@ -646,7 +646,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy, - (CARD32)(-1), -1); + (uint32_t)(-1), -1); for (; nbox-- ; pbox++) { int xa = pbox->x1; @@ -724,7 +724,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) unsigned int device = drmAgpDeviceId(info->drmFD); /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with pcie-agp rialto bridge chip - use the one from bridge which must match */ - CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; + uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); unsigned int defaultMode; MessageType from; @@ -1903,7 +1903,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) #ifdef USE_EXA if (info->useEXA) { - CARD32 src_pitch_offset, dst_pitch_offset, datatype; + uint32_t src_pitch_offset, dst_pitch_offset, datatype; RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10); @@ -1924,7 +1924,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; (*info->accel->SetupForScreenToScreenCopy)(pScrn, 1, 1, GXcopy, - (CARD32)(-1), -1); + (uint32_t)(-1), -1); } #endif diff --git a/src/radeon_driver.c b/src/radeon_driver.c index b04e48fc..d4d95cf7 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -204,17 +204,17 @@ static int getRADEONEntityIndex(void) } struct RADEONInt10Save { - CARD32 MEM_CNTL; - CARD32 MEMSIZE; - CARD32 MPP_TB_CONFIG; + uint32_t MEM_CNTL; + uint32_t MEMSIZE; + uint32_t MPP_TB_CONFIG; }; static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); static void * -radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, - CARD32 *size, void *closure) +radeonShadowWindow(ScreenPtr screen, uint32_t row, uint32_t offset, int mode, + uint32_t *size, void *closure) { ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -223,7 +223,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; - return ((CARD8 *)info->FB + pScrn->fbOffset + + return ((uint8_t *)info->FB + pScrn->fbOffset + row * stride + offset); } static Bool @@ -262,8 +262,8 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 CardTmp; - static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; + uint32_t CardTmp; + static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; if (!IS_AVIVO_VARIANT) { /* Save the values and zap MEM_CNTL */ @@ -289,7 +289,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; struct RADEONInt10Save *pSave = ptr; - CARD32 CardTmp; + uint32_t CardTmp; /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ if (!pSave || !pSave->MEM_CNTL) @@ -527,7 +527,7 @@ void RADEONPllErrataAfterData(RADEONInfoPtr info) * may not be correct. */ if (info->ChipErrata & CHIP_ERRATA_R300_CG) { - CARD32 save, tmp; + uint32_t save, tmp; save = INREG(RADEON_CLOCK_CNTL_INDEX); tmp = save & ~(0x3f | RADEON_PLL_WR_EN); @@ -542,7 +542,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 data; + uint32_t data; OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); RADEONPllErrataAfterIndex(info); @@ -553,7 +553,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) } /* Write PLL information */ -void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) +void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -570,7 +570,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 data; + uint32_t data; if ((info->ChipFamily == CHIP_FAMILY_RS690) || (info->ChipFamily == CHIP_FAMILY_RS740)) { @@ -596,7 +596,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) } /* Write MC information */ -void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) +void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -651,7 +651,7 @@ static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) #define LOC_FB 0x1 #define LOC_AGP 0x2 -static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi) +static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -689,7 +689,7 @@ static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 } } -static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi) +static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -748,7 +748,7 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 crtc_gen_cntl; + uint32_t crtc_gen_cntl; struct timeval timeout; crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); @@ -771,7 +771,7 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 crtc2_gen_cntl; + uint32_t crtc2_gen_cntl; struct timeval timeout; crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); @@ -942,7 +942,7 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) /* Some sanity check based on the BIOS code .... */ if (ref_div < 2) { - CARD32 tmp; + uint32_t tmp; tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_RS400)) @@ -1021,7 +1021,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) We'll probably need a new routine to calculate the best ref_div from BIOS provided min_input_pll and max_input_pll */ - CARD32 tmp; + uint32_t tmp; tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300) || @@ -1216,8 +1216,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 mem_size; - CARD32 aper_size; + uint32_t mem_size; + uint32_t aper_size; radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, &info->mc_agp_location, &info->mc_agp_location_hi); @@ -1262,7 +1262,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) else #endif { - CARD32 aper0_base; + uint32_t aper0_base; if (info->ChipFamily >= CHIP_FAMILY_R600) { aper0_base = INREG(R600_CONFIG_F0_BASE); @@ -1329,7 +1329,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; + uint32_t tmp; if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) @@ -1370,11 +1370,11 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) * accessible to the CPU can vary. This function is our best shot at figuring * it out. Returns a value in KB. */ -static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) +static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 aper_size; + uint32_t aper_size; unsigned char byte; if (info->ChipFamily >= CHIP_FAMILY_R600) @@ -1447,10 +1447,10 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) GDevPtr dev = pEnt->device; unsigned char *RADEONMMIO = info->MMIO; MessageType from = X_PROBED; - CARD32 accessible, bar_size; + uint32_t accessible, bar_size; if ((!IS_AVIVO_VARIANT) && info->IsIGP) { - CARD32 tom = INREG(RADEON_NB_TOM); + uint32_t tom = INREG(RADEON_NB_TOM); pScrn->videoRam = (((tom >> 16) - (tom & 0xffff) + 1) << 6); @@ -1947,7 +1947,7 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) #if !defined(__powerpc__) && !defined(__sparc__) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 fp2_gen_ctl_save = 0; + uint32_t fp2_gen_ctl_save = 0; if (xf86LoadSubModule(pScrn, "int10")) { /* The VGA BIOS on the RV100/QY cannot be read when the digital output @@ -2251,9 +2251,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD16 mm_table; - CARD16 bios_header; - CARD16 pll_info_block; + uint16_t mm_table; + uint16_t bios_header; + uint16_t pll_info_block; #ifdef XvExtension char* microc_path = NULL; char* microc_type = NULL; @@ -2879,7 +2879,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; int index, j; - CARD16 lut_r[256], lut_g[256], lut_b[256]; + uint16_t lut_r[256], lut_g[256], lut_b[256]; int c; #ifdef XF86DRI @@ -3552,7 +3552,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; int timeout; - CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; + uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, &mc_agp_loc, &mc_agp_loc_hi); @@ -3572,7 +3572,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { - CARD32 tmp; + uint32_t tmp; RADEONWaitForIdleMMIO(pScrn); @@ -3628,8 +3628,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, */ if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { - CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; - CARD32 old_mc_status, status_idle; + uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; + uint32_t old_mc_status, status_idle; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, " Map Changed ! Applying ...\n"); @@ -3767,7 +3767,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 fb, agp, agp_hi; + uint32_t fb, agp, agp_hi; int changed = 0; if (info->IsSecondary) @@ -5444,7 +5444,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) { /* It appears from r300 and rv100 may need some clocks forced-on */ - CARD32 tmp; + uint32_t tmp; tmp = INPLL(pScrn, RADEON_SCLK_CNTL); tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; @@ -5456,7 +5456,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; + uint32_t tmp; switch(mode) { case 0: /* Turn everything OFF (ForceON to everything)*/ if ( !pRADEONEnt->HasCRTC2 ) { diff --git a/src/radeon_exa.c b/src/radeon_exa.c index fa6ac0d9..0193a289 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -112,11 +112,11 @@ RADEONLog2(int val) #endif } -static __inline__ CARD32 F_TO_DW(float val) +static __inline__ uint32_t F_TO_DW(float val) { union { float f; - CARD32 l; + uint32_t l; } tmp; tmp.f = val; return tmp.l; @@ -125,7 +125,7 @@ static __inline__ CARD32 F_TO_DW(float val) /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we * require src and dest datatypes to be equal. */ -Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type) +Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) { switch (bpp) { case 8: @@ -159,7 +159,7 @@ static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) return FALSE; } -static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, +static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, unsigned int offset, unsigned int pitch) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); @@ -179,10 +179,10 @@ static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, return TRUE; } -Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset) +Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); - CARD32 pitch, offset; + uint32_t pitch, offset; int bpp; bpp = pPix->drawable.bitsPerPixel; @@ -203,9 +203,9 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); unsigned char *RADEONMMIO = info->MMIO; - CARD32 offset = exaGetPixmapOffset(pPix); + uint32_t offset = exaGetPixmapOffset(pPix); int bpp, soff; - CARD32 size, flags; + uint32_t size, flags; /* Front buffer is always set with proper swappers */ if (offset == 0) @@ -269,7 +269,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); unsigned char *RADEONMMIO = info->MMIO; - CARD32 offset = exaGetPixmapOffset(pPix); + uint32_t offset = exaGetPixmapOffset(pPix); int soff; /* Front buffer is always set with proper swappers */ @@ -300,7 +300,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #define RADEON_SWITCH_TO_2D() \ do { \ - CARD32 wait_until = 0; \ + uint32_t wait_until = 0; \ BEGIN_ACCEL(1); \ switch (info->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ @@ -317,7 +317,7 @@ do { \ #define RADEON_SWITCH_TO_3D() \ do { \ - CARD32 wait_until = 0; \ + uint32_t wait_until = 0; \ BEGIN_ACCEL(1); \ switch (info->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index 1a55e28e..80f3be9d 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -88,7 +88,7 @@ static Bool FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); - CARD32 datatype, dst_pitch_offset; + uint32_t datatype, dst_pitch_offset; ACCEL_PREAMBLE(); TRACE; @@ -143,8 +143,8 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) } void -FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, CARD32 src_pitch_offset, - CARD32 dst_pitch_offset, CARD32 datatype, int rop, +FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, + uint32_t dst_pitch_offset, uint32_t datatype, int rop, Pixel planemask) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -178,7 +178,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, Pixel planemask) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); - CARD32 datatype, src_pitch_offset, dst_pitch_offset; + uint32_t datatype, src_pitch_offset, dst_pitch_offset; TRACE; @@ -241,12 +241,12 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); - CARD8 *dst = info->FB + exaGetPixmapOffset(pDst); + uint8_t *dst = info->FB + exaGetPixmapOffset(pDst); unsigned int dst_pitch = exaGetPixmapPitch(pDst); unsigned int bpp = pDst->drawable.bitsPerPixel; #ifdef ACCEL_CP unsigned int hpass; - CARD32 buf_pitch, dst_pitch_off; + uint32_t buf_pitch, dst_pitch_off; #endif #if X_BYTE_ORDER == X_BIG_ENDIAN unsigned char *RADEONMMIO = info->MMIO; @@ -263,7 +263,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, #ifdef ACCEL_CP if (info->directRenderingEnabled && RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) { - CARD8 *buf; + uint8_t *buf; int cpp = bpp / 8; ACCEL_PREAMBLE(); @@ -271,7 +271,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, while ((buf = RADEONHostDataBlit(pScrn, cpp, w, dst_pitch_off, &buf_pitch, x, &y, (unsigned int*)&h, &hpass)) != 0) { - RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (CARD8 *)src, + RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (uint8_t *)src, hpass, buf_pitch, src_pitch); src += hpass * src_pitch; } @@ -319,8 +319,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, #ifdef ACCEL_CP /* Emit blit with arbitrary source and destination offsets and pitches */ static void -RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset, - CARD32 dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, +RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, + uint32_t dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, int w, int h) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -357,11 +357,11 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); #endif - CARD8 *src = info->FB + exaGetPixmapOffset(pSrc); + uint8_t *src = info->FB + exaGetPixmapOffset(pSrc); int src_pitch = exaGetPixmapPitch(pSrc); int bpp = pSrc->drawable.bitsPerPixel; #ifdef ACCEL_CP - CARD32 datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; + uint32_t datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; drmBufPtr scratch; #endif @@ -379,7 +379,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, { int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; int hpass = min(h, scratch->total/2 / scratch_pitch); - CARD32 scratch_pitch_offset = scratch_pitch << 16 + uint32_t scratch_pitch_offset = scratch_pitch << 16 | (info->gartLocation + info->bufStart + scratch->idx * scratch->total) >> 10; drmRadeonIndirect indirect; @@ -406,7 +406,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, while (h) { int oldhpass = hpass, i = 0; - src = (CARD8*)scratch->address + scratch_off; + src = (uint8_t*)scratch->address + scratch_off; y += oldhpass; h -= oldhpass; @@ -439,10 +439,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, /* Copy out data from previous blit */ if (wpass == scratch_pitch && wpass == dst_pitch) { - RADEONCopySwap((CARD8*)dst, src, wpass * oldhpass, swap); + RADEONCopySwap((uint8_t*)dst, src, wpass * oldhpass, swap); dst += dst_pitch * oldhpass; } else while (oldhpass--) { - RADEONCopySwap((CARD8*)dst, src, wpass, swap); + RADEONCopySwap((uint8_t*)dst, src, wpass, swap); src += scratch_pitch; dst += dst_pitch; } diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 54b02720..f519a3e2 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -69,7 +69,7 @@ static Bool src_tile_height; struct blendinfo { Bool dst_alpha; Bool src_alpha; - CARD32 blend_cntl; + uint32_t blend_cntl; }; static struct blendinfo RadeonBlendOp[] = { @@ -103,7 +103,7 @@ static struct blendinfo RadeonBlendOp[] = { struct formatinfo { int fmt; - CARD32 card_fmt; + uint32_t card_fmt; }; /* Note on texture formats: @@ -142,7 +142,7 @@ static struct formatinfo R300TexFormats[] = { /* Common Radeon setup code */ -static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) +static Bool RADEONGetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: @@ -167,7 +167,7 @@ static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) return TRUE; } -static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) +static Bool R300GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: @@ -191,9 +191,9 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) return TRUE; } -static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) +static uint32_t RADEONGetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) { - CARD32 sblend, dblend; + uint32_t sblend, dblend; sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; @@ -225,7 +225,7 @@ static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) union intfloat { float f; - CARD32 i; + uint32_t i; }; /* Check if we need a software-fallback because of a repeating @@ -258,7 +258,7 @@ static Bool RADEONPitchMatches(PixmapPtr pPix) { int w = pPix->drawable.width; int h = pPix->drawable.height; - CARD32 txpitch = exaGetPixmapPitch(pPix); + uint32_t txpitch = exaGetPixmapPitch(pPix); if (h > 1 && ((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch) return FALSE; @@ -354,7 +354,7 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); - CARD32 txfilter, txformat, txoffset, txpitch; + uint32_t txfilter, txformat, txoffset, txpitch; int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); @@ -451,7 +451,7 @@ static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { PixmapPtr pSrcPixmap, pDstPixmap; - CARD32 tmp1; + uint32_t tmp1; /* Check for unsupported compositing operations. */ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) @@ -524,8 +524,8 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); - CARD32 dst_format, dst_offset, dst_pitch, colorpitch; - CARD32 pp_cntl, blendcntl, cblend, ablend; + uint32_t dst_format, dst_offset, dst_pitch, colorpitch; + uint32_t pp_cntl, blendcntl, cblend, ablend; int pixel_shift; ACCEL_PREAMBLE(); @@ -667,7 +667,7 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); - CARD32 txfilter, txformat, txoffset, txpitch; + uint32_t txfilter, txformat, txoffset, txpitch; int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); @@ -756,7 +756,7 @@ static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP PicturePtr pDstPicture) { PixmapPtr pSrcPixmap, pDstPixmap; - CARD32 tmp1; + uint32_t tmp1; TRACE; @@ -823,8 +823,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); - CARD32 dst_format, dst_offset, dst_pitch; - CARD32 pp_cntl, blendcntl, cblend, ablend, colorpitch; + uint32_t dst_format, dst_offset, dst_pitch; + uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; int pixel_shift; ACCEL_PREAMBLE(); @@ -992,7 +992,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); - CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; + uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; int i, pixel_shift; @@ -1091,7 +1091,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { - CARD32 tmp1; + uint32_t tmp1; ScreenPtr pScreen = pDstPicture->pDrawable->pScreen; PixmapPtr pSrcPixmap, pDstPixmap; ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -1177,9 +1177,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); - CARD32 dst_format, dst_offset, dst_pitch; - CARD32 txenable, colorpitch; - CARD32 blendcntl; + uint32_t dst_format, dst_offset, dst_pitch; + uint32_t txenable, colorpitch; + uint32_t blendcntl; int pixel_shift; ACCEL_PREAMBLE(); @@ -1324,7 +1324,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, /* setup pixel shader */ if (IS_R300_3D) { - CARD32 output_fmt; + uint32_t output_fmt; int src_color, src_alpha; int mask_color, mask_alpha; @@ -1520,9 +1520,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R300_ALU_ALPHA_CLAMP)); FINISH_ACCEL(); } else { - CARD32 output_fmt; - CARD32 src_color, src_alpha; - CARD32 mask_color, mask_alpha; + uint32_t output_fmt; + uint32_t src_color, src_alpha; + uint32_t mask_color, mask_alpha; if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) src_color = (R500_ALU_RGB_R_SWIZ_A_0 | diff --git a/src/radeon_macros.h b/src/radeon_macros.h index 7f532a84..f19bc3e7 100644 --- a/src/radeon_macros.h +++ b/src/radeon_macros.h @@ -67,12 +67,12 @@ #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) -#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr))) +#define ADDRREG(addr) ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr))) #define OUTREGP(addr, val, mask) \ do { \ - CARD32 tmp = INREG(addr); \ + uint32_t tmp = INREG(addr); \ tmp &= (mask); \ tmp |= ((val) & ~(mask)); \ OUTREG(addr, tmp); \ @@ -84,7 +84,7 @@ do { \ #define OUTPLLP(pScrn, addr, val, mask) \ do { \ - CARD32 tmp_ = INPLL(pScrn, addr); \ + uint32_t tmp_ = INPLL(pScrn, addr); \ tmp_ &= (mask); \ tmp_ |= ((val) & ~(mask)); \ OUTPLL(pScrn, addr, tmp_); \ @@ -108,7 +108,7 @@ do { \ } \ } while (0) -#define OUTPAL_NEXT_CARD32(v) \ +#define OUTPAL_NEXT_uint32_t(v) \ do { \ OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ } while (0) @@ -148,7 +148,7 @@ do { \ } else { \ if (!idx) { \ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ - (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ + (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL); \ } else { \ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ RADEON_DAC2_PALETTE_ACC_CTL); \ diff --git a/src/radeon_mm_i2c.c b/src/radeon_mm_i2c.c index 0524fa9c..bb454073 100644 --- a/src/radeon_mm_i2c.c +++ b/src/radeon_mm_i2c.c @@ -64,9 +64,9 @@ static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv); * I2C_NACK - an NACK was received from the slave * * I2C_HALT - a timeout condition has occured * ****************************************************************************/ -static CARD8 RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) +static uint8_t RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { - CARD8 retval = 0; + uint8_t retval = 0; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; long counter = 0; @@ -103,7 +103,7 @@ static void RADEON_I2C_Halt (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD8 reg; + uint8_t reg; /* reset status flags */ RADEONWaitForIdleMMIO(pScrn); @@ -124,8 +124,8 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, I2CByte *ReadBuffer, int nRead) { int loop, status; - CARD32 i2c_cntl_0, i2c_cntl_1; - CARD8 reg; + uint32_t i2c_cntl_0, i2c_cntl_1; + uint8_t reg; RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -141,7 +141,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); + OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); /* Write Value into the buffer */ for (loop = 0; loop < nWrite; loop++) @@ -172,7 +172,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); + OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | nRead | 0x100; @@ -209,8 +209,8 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, I2CByte *ReadBuffer, int nRead) { int loop, status; - CARD32 i2c_cntl_0, i2c_cntl_1; - CARD8 reg; + uint32_t i2c_cntl_0, i2c_cntl_1; + uint8_t reg; RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -226,7 +226,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); + OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); /* Write Value into the buffer */ for (loop = 0; loop < nWrite; loop++) @@ -257,7 +257,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); + OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | nRead | 0x010; diff --git a/src/radeon_output.c b/src/radeon_output.c index 9b2494b8..f5d82cb8 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -145,7 +145,7 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ }; -static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = +static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = { 0x00000000, /* unknown */ 0x00000000, /* legacy */ @@ -252,7 +252,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 DDCReg; + uint32_t DDCReg; RADEONMonitorType MonType = MT_NONE; xf86MonPtr MonInfo = NULL; RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -266,7 +266,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) /* Read and output monitor info using DDC2 over I2C bus */ if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { OUTREG(DDCReg, INREG(DDCReg) & - (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); + (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); /* For some old monitors (like Compaq Presario FP500), we need * following process to initialize/stop DDC @@ -1154,7 +1154,7 @@ radeon_set_backlight_level(xf86OutputPtr output, int level) ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char * RADEONMMIO = info->MMIO; - CARD32 lvds_gen_cntl; + uint32_t lvds_gen_cntl; lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; @@ -1730,7 +1730,7 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) RADEONOutputPrivatePtr radeon_output = output->driver_private; RADEONI2CBusPtr pRADEONI2CBus = radeon_output->pI2CBus->DriverPrivate.ptr; unsigned char *RADEONMMIO = info->MMIO; - CARD32 temp; + uint32_t temp; temp = INREG(pRADEONI2CBus->mask_clk_reg); if (lock_state == AVIVO_I2C_ENABLE) @@ -1775,13 +1775,13 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) unsigned char *RADEONMMIO = info->MMIO; RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; - val = INREG(pRADEONI2CBus->put_clk_reg) & (CARD32)~(pRADEONI2CBus->put_clk_mask); + val = INREG(pRADEONI2CBus->put_clk_reg) & (uint32_t)~(pRADEONI2CBus->put_clk_mask); val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask); OUTREG(pRADEONI2CBus->put_clk_reg, val); /* read back to improve reliability on some cards. */ val = INREG(pRADEONI2CBus->put_clk_reg); - val = INREG(pRADEONI2CBus->put_data_reg) & (CARD32)~(pRADEONI2CBus->put_data_mask); + val = INREG(pRADEONI2CBus->put_data_reg) & (uint32_t)~(pRADEONI2CBus->put_data_mask); val |= (data ? 0:pRADEONI2CBus->put_data_mask); OUTREG(pRADEONI2CBus->put_data_reg, val); /* read back to improve reliability on some cards. */ @@ -1898,8 +1898,8 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; unsigned char *RADEONMMIO = info->MMIO; - CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); - CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); + uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); + uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); radeon_output->PanelPwrDly = 200; if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { @@ -1922,7 +1922,7 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) // move this to crtc function if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { - CARD32 ppll_div_sel, ppll_val; + uint32_t ppll_div_sel, ppll_val; ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; RADEONPllErrataAfterIndex(info); diff --git a/src/radeon_probe.h b/src/radeon_probe.h index f03e9970..24af52b3 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -123,8 +123,8 @@ typedef enum } RADEONRMXType; typedef struct { - CARD32 freq; - CARD32 value; + uint32_t freq; + uint32_t value; }RADEONTMDSPll; typedef enum @@ -164,18 +164,18 @@ typedef enum typedef struct { Bool valid; - CARD32 mask_clk_reg; - CARD32 mask_data_reg; - CARD32 put_clk_reg; - CARD32 put_data_reg; - CARD32 get_clk_reg; - CARD32 get_data_reg; - CARD32 mask_clk_mask; - CARD32 mask_data_mask; - CARD32 put_clk_mask; - CARD32 put_data_mask; - CARD32 get_clk_mask; - CARD32 get_data_mask; + uint32_t mask_clk_reg; + uint32_t mask_data_reg; + uint32_t put_clk_reg; + uint32_t put_data_reg; + uint32_t get_clk_reg; + uint32_t get_data_reg; + uint32_t mask_clk_mask; + uint32_t mask_data_mask; + uint32_t put_clk_mask; + uint32_t put_data_mask; + uint32_t get_clk_mask; + uint32_t get_data_mask; } RADEONI2CBusRec, *RADEONI2CBusPtr; typedef struct _RADEONCrtcPrivateRec { @@ -187,9 +187,9 @@ typedef struct _RADEONCrtcPrivateRec { #endif int crtc_id; int binding; - CARD32 cursor_offset; + uint32_t cursor_offset; /* Lookup table values to be set when the CRTC is enabled */ - CARD8 lut_r[256], lut_g[256], lut_b[256]; + uint8_t lut_r[256], lut_g[256], lut_b[256]; uint32_t crtc_offset; int can_tile; @@ -212,7 +212,7 @@ typedef struct _RADEONOutputPrivateRec { int num; RADEONOutputType type; void *dev_priv; - CARD32 ddc_line; + uint32_t ddc_line; RADEONDacType DACType; RADEONDviType DVIType; RADEONTmdsType TMDSType; @@ -222,9 +222,9 @@ typedef struct _RADEONOutputPrivateRec { int DDCReg; I2CBusPtr pI2CBus; RADEONI2CBusRec ddc_i2c; - CARD32 ps2_tvdac_adj; - CARD32 pal_tvdac_adj; - CARD32 ntsc_tvdac_adj; + uint32_t ps2_tvdac_adj; + uint32_t pal_tvdac_adj; + uint32_t ntsc_tvdac_adj; /* panel stuff */ int PanelXRes; int PanelYRes; @@ -266,66 +266,66 @@ typedef struct _RADEONOutputPrivateRec { } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; struct avivo_pll_state { - CARD32 ref_div_src; - CARD32 ref_div; - CARD32 fb_div; - CARD32 post_div_src; - CARD32 post_div; - CARD32 ext_ppll_cntl; - CARD32 pll_cntl; - CARD32 int_ss_cntl; + uint32_t ref_div_src; + uint32_t ref_div; + uint32_t fb_div; + uint32_t post_div_src; + uint32_t post_div; + uint32_t ext_ppll_cntl; + uint32_t pll_cntl; + uint32_t int_ss_cntl; }; struct avivo_crtc_state { - CARD32 pll_source; - CARD32 h_total; - CARD32 h_blank_start_end; - CARD32 h_sync_a; - CARD32 h_sync_a_cntl; - CARD32 h_sync_b; - CARD32 h_sync_b_cntl; - CARD32 v_total; - CARD32 v_blank_start_end; - CARD32 v_sync_a; - CARD32 v_sync_a_cntl; - CARD32 v_sync_b; - CARD32 v_sync_b_cntl; - CARD32 control; - CARD32 blank_control; - CARD32 interlace_control; - CARD32 stereo_control; - CARD32 cursor_control; + uint32_t pll_source; + uint32_t h_total; + uint32_t h_blank_start_end; + uint32_t h_sync_a; + uint32_t h_sync_a_cntl; + uint32_t h_sync_b; + uint32_t h_sync_b_cntl; + uint32_t v_total; + uint32_t v_blank_start_end; + uint32_t v_sync_a; + uint32_t v_sync_a_cntl; + uint32_t v_sync_b; + uint32_t v_sync_b_cntl; + uint32_t control; + uint32_t blank_control; + uint32_t interlace_control; + uint32_t stereo_control; + uint32_t cursor_control; }; struct avivo_grph_state { - CARD32 enable; - CARD32 control; - CARD32 prim_surf_addr; - CARD32 sec_surf_addr; - CARD32 pitch; - CARD32 x_offset; - CARD32 y_offset; - CARD32 x_start; - CARD32 y_start; - CARD32 x_end; - CARD32 y_end; - - CARD32 viewport_start; - CARD32 viewport_size; + uint32_t enable; + uint32_t control; + uint32_t prim_surf_addr; + uint32_t sec_surf_addr; + uint32_t pitch; + uint32_t x_offset; + uint32_t y_offset; + uint32_t x_start; + uint32_t y_start; + uint32_t x_end; + uint32_t y_end; + + uint32_t viewport_start; + uint32_t viewport_size; }; struct avivo_state { - CARD32 hdp_fb_location; - CARD32 mc_memory_map; - CARD32 vga_memory_base; - CARD32 vga_fb_start; + uint32_t hdp_fb_location; + uint32_t mc_memory_map; + uint32_t vga_memory_base; + uint32_t vga_fb_start; - CARD32 vga1_cntl; - CARD32 vga2_cntl; + uint32_t vga1_cntl; + uint32_t vga2_cntl; - CARD32 crtc_master_en; - CARD32 crtc_tv_control; + uint32_t crtc_master_en; + uint32_t crtc_tv_control; struct avivo_pll_state pll1; struct avivo_pll_state pll2; @@ -337,40 +337,40 @@ struct avivo_state struct avivo_grph_state grph2; /* DDIA block on RS6xx chips */ - CARD32 ddia[37]; + uint32_t ddia[37]; /* scalers */ - CARD32 d1scl[40]; - CARD32 d2scl[40]; - CARD32 dxscl[6+2]; + uint32_t d1scl[40]; + uint32_t d2scl[40]; + uint32_t dxscl[6+2]; /* dac regs */ - CARD32 daca[26]; - CARD32 dacb[26]; + uint32_t daca[26]; + uint32_t dacb[26]; /* tmdsa */ - CARD32 tmdsa[31]; + uint32_t tmdsa[31]; /* lvtma */ - CARD32 lvtma[39]; + uint32_t lvtma[39]; /* dvoa */ - CARD32 dvoa[16]; + uint32_t dvoa[16]; /* DCE3 chips */ - CARD32 fmt1[18]; - CARD32 fmt2[18]; - CARD32 dig1[19]; - CARD32 dig2[19]; - CARD32 hdmi1[57]; - CARD32 hdmi2[57]; - CARD32 aux_cntl1[14]; - CARD32 aux_cntl2[14]; - CARD32 aux_cntl3[14]; - CARD32 aux_cntl4[14]; - CARD32 phy[10]; - CARD32 uniphy1[8]; - CARD32 uniphy2[8]; + uint32_t fmt1[18]; + uint32_t fmt2[18]; + uint32_t dig1[19]; + uint32_t dig2[19]; + uint32_t hdmi1[57]; + uint32_t hdmi2[57]; + uint32_t aux_cntl1[14]; + uint32_t aux_cntl2[14]; + uint32_t aux_cntl3[14]; + uint32_t aux_cntl4[14]; + uint32_t phy[10]; + uint32_t uniphy1[8]; + uint32_t uniphy2[8]; }; @@ -384,100 +384,100 @@ typedef struct { struct avivo_state avivo; /* Common registers */ - CARD32 ovr_clr; - CARD32 ovr_wid_left_right; - CARD32 ovr_wid_top_bottom; - CARD32 ov0_scale_cntl; - CARD32 mpp_tb_config; - CARD32 mpp_gp_config; - CARD32 subpic_cntl; - CARD32 viph_control; - CARD32 i2c_cntl_1; - CARD32 gen_int_cntl; - CARD32 cap0_trig_cntl; - CARD32 cap1_trig_cntl; - CARD32 bus_cntl; - - CARD32 bios_0_scratch; - CARD32 bios_1_scratch; - CARD32 bios_2_scratch; - CARD32 bios_3_scratch; - CARD32 bios_4_scratch; - CARD32 bios_5_scratch; - CARD32 bios_6_scratch; - CARD32 bios_7_scratch; - - CARD32 surface_cntl; - CARD32 surfaces[8][3]; - CARD32 mc_agp_location; - CARD32 mc_agp_location_hi; - CARD32 mc_fb_location; - CARD32 display_base_addr; - CARD32 display2_base_addr; - CARD32 ov0_base_addr; + uint32_t ovr_clr; + uint32_t ovr_wid_left_right; + uint32_t ovr_wid_top_bottom; + uint32_t ov0_scale_cntl; + uint32_t mpp_tb_config; + uint32_t mpp_gp_config; + uint32_t subpic_cntl; + uint32_t viph_control; + uint32_t i2c_cntl_1; + uint32_t gen_int_cntl; + uint32_t cap0_trig_cntl; + uint32_t cap1_trig_cntl; + uint32_t bus_cntl; + + uint32_t bios_0_scratch; + uint32_t bios_1_scratch; + uint32_t bios_2_scratch; + uint32_t bios_3_scratch; + uint32_t bios_4_scratch; + uint32_t bios_5_scratch; + uint32_t bios_6_scratch; + uint32_t bios_7_scratch; + + uint32_t surface_cntl; + uint32_t surfaces[8][3]; + uint32_t mc_agp_location; + uint32_t mc_agp_location_hi; + uint32_t mc_fb_location; + uint32_t display_base_addr; + uint32_t display2_base_addr; + uint32_t ov0_base_addr; /* Other registers to save for VT switches */ - CARD32 dp_datatype; - CARD32 rbbm_soft_reset; - CARD32 clock_cntl_index; - CARD32 amcgpio_en_reg; - CARD32 amcgpio_mask; + uint32_t dp_datatype; + uint32_t rbbm_soft_reset; + uint32_t clock_cntl_index; + uint32_t amcgpio_en_reg; + uint32_t amcgpio_mask; /* CRTC registers */ - CARD32 crtc_gen_cntl; - CARD32 crtc_ext_cntl; - CARD32 dac_cntl; - CARD32 crtc_h_total_disp; - CARD32 crtc_h_sync_strt_wid; - CARD32 crtc_v_total_disp; - CARD32 crtc_v_sync_strt_wid; - CARD32 crtc_offset; - CARD32 crtc_offset_cntl; - CARD32 crtc_pitch; - CARD32 disp_merge_cntl; - CARD32 grph_buffer_cntl; - CARD32 crtc_more_cntl; - CARD32 crtc_tile_x0_y0; + uint32_t crtc_gen_cntl; + uint32_t crtc_ext_cntl; + uint32_t dac_cntl; + uint32_t crtc_h_total_disp; + uint32_t crtc_h_sync_strt_wid; + uint32_t crtc_v_total_disp; + uint32_t crtc_v_sync_strt_wid; + uint32_t crtc_offset; + uint32_t crtc_offset_cntl; + uint32_t crtc_pitch; + uint32_t disp_merge_cntl; + uint32_t grph_buffer_cntl; + uint32_t crtc_more_cntl; + uint32_t crtc_tile_x0_y0; /* CRTC2 registers */ - CARD32 crtc2_gen_cntl; - CARD32 dac_macro_cntl; - CARD32 dac2_cntl; - CARD32 disp_output_cntl; - CARD32 disp_tv_out_cntl; - CARD32 disp_hw_debug; - CARD32 disp2_merge_cntl; - CARD32 grph2_buffer_cntl; - CARD32 crtc2_h_total_disp; - CARD32 crtc2_h_sync_strt_wid; - CARD32 crtc2_v_total_disp; - CARD32 crtc2_v_sync_strt_wid; - CARD32 crtc2_offset; - CARD32 crtc2_offset_cntl; - CARD32 crtc2_pitch; - CARD32 crtc2_tile_x0_y0; + uint32_t crtc2_gen_cntl; + uint32_t dac_macro_cntl; + uint32_t dac2_cntl; + uint32_t disp_output_cntl; + uint32_t disp_tv_out_cntl; + uint32_t disp_hw_debug; + uint32_t disp2_merge_cntl; + uint32_t grph2_buffer_cntl; + uint32_t crtc2_h_total_disp; + uint32_t crtc2_h_sync_strt_wid; + uint32_t crtc2_v_total_disp; + uint32_t crtc2_v_sync_strt_wid; + uint32_t crtc2_offset; + uint32_t crtc2_offset_cntl; + uint32_t crtc2_pitch; + uint32_t crtc2_tile_x0_y0; /* Flat panel registers */ - CARD32 fp_crtc_h_total_disp; - CARD32 fp_crtc_v_total_disp; - CARD32 fp_gen_cntl; - CARD32 fp2_gen_cntl; - CARD32 fp_h_sync_strt_wid; - CARD32 fp_h2_sync_strt_wid; - CARD32 fp_horz_stretch; - CARD32 fp_horz_vert_active; - CARD32 fp_panel_cntl; - CARD32 fp_v_sync_strt_wid; - CARD32 fp_v2_sync_strt_wid; - CARD32 fp_vert_stretch; - CARD32 lvds_gen_cntl; - CARD32 lvds_pll_cntl; - CARD32 tmds_pll_cntl; - CARD32 tmds_transmitter_cntl; + uint32_t fp_crtc_h_total_disp; + uint32_t fp_crtc_v_total_disp; + uint32_t fp_gen_cntl; + uint32_t fp2_gen_cntl; + uint32_t fp_h_sync_strt_wid; + uint32_t fp_h2_sync_strt_wid; + uint32_t fp_horz_stretch; + uint32_t fp_horz_vert_active; + uint32_t fp_panel_cntl; + uint32_t fp_v_sync_strt_wid; + uint32_t fp_v2_sync_strt_wid; + uint32_t fp_vert_stretch; + uint32_t lvds_gen_cntl; + uint32_t lvds_pll_cntl; + uint32_t tmds_pll_cntl; + uint32_t tmds_transmitter_cntl; /* Computed values for PLL */ - CARD32 dot_clock_freq; - CARD32 pll_output_freq; + uint32_t dot_clock_freq; + uint32_t pll_output_freq; int feedback_div; int reference_div; int post_div; @@ -485,81 +485,81 @@ typedef struct { /* PLL registers */ unsigned ppll_ref_div; unsigned ppll_div_3; - CARD32 htotal_cntl; - CARD32 vclk_ecp_cntl; + uint32_t htotal_cntl; + uint32_t vclk_ecp_cntl; /* Computed values for PLL2 */ - CARD32 dot_clock_freq_2; - CARD32 pll_output_freq_2; + uint32_t dot_clock_freq_2; + uint32_t pll_output_freq_2; int feedback_div_2; int reference_div_2; int post_div_2; /* PLL2 registers */ - CARD32 p2pll_ref_div; - CARD32 p2pll_div_0; - CARD32 htotal_cntl2; - CARD32 pixclks_cntl; + uint32_t p2pll_ref_div; + uint32_t p2pll_div_0; + uint32_t htotal_cntl2; + uint32_t pixclks_cntl; /* Pallet */ Bool palette_valid; - CARD32 palette[256]; - CARD32 palette2[256]; + uint32_t palette[256]; + uint32_t palette2[256]; - CARD32 disp2_req_cntl1; - CARD32 disp2_req_cntl2; - CARD32 dmif_mem_cntl1; - CARD32 disp1_req_cntl1; + uint32_t disp2_req_cntl1; + uint32_t disp2_req_cntl2; + uint32_t dmif_mem_cntl1; + uint32_t disp1_req_cntl1; - CARD32 fp_2nd_gen_cntl; - CARD32 fp2_2_gen_cntl; - CARD32 tmds2_cntl; - CARD32 tmds2_transmitter_cntl; + uint32_t fp_2nd_gen_cntl; + uint32_t fp2_2_gen_cntl; + uint32_t tmds2_cntl; + uint32_t tmds2_transmitter_cntl; /* TV out registers */ - CARD32 tv_master_cntl; - CARD32 tv_htotal; - CARD32 tv_hsize; - CARD32 tv_hdisp; - CARD32 tv_hstart; - CARD32 tv_vtotal; - CARD32 tv_vdisp; - CARD32 tv_timing_cntl; - CARD32 tv_vscaler_cntl1; - CARD32 tv_vscaler_cntl2; - CARD32 tv_sync_size; - CARD32 tv_vrestart; - CARD32 tv_hrestart; - CARD32 tv_frestart; - CARD32 tv_ftotal; - CARD32 tv_clock_sel_cntl; - CARD32 tv_clkout_cntl; - CARD32 tv_data_delay_a; - CARD32 tv_data_delay_b; - CARD32 tv_dac_cntl; - CARD32 tv_pll_cntl; - CARD32 tv_pll_cntl1; - CARD32 tv_pll_fine_cntl; - CARD32 tv_modulator_cntl1; - CARD32 tv_modulator_cntl2; - CARD32 tv_frame_lock_cntl; - CARD32 tv_pre_dac_mux_cntl; - CARD32 tv_rgb_cntl; - CARD32 tv_y_saw_tooth_cntl; - CARD32 tv_y_rise_cntl; - CARD32 tv_y_fall_cntl; - CARD32 tv_uv_adr; - CARD32 tv_upsamp_and_gain_cntl; - CARD32 tv_gain_limit_settings; - CARD32 tv_linear_gain_settings; - CARD32 tv_crc_cntl; - CARD32 tv_sync_cntl; - CARD32 gpiopad_a; - CARD32 pll_test_cntl; - - CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; - CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; + uint32_t tv_master_cntl; + uint32_t tv_htotal; + uint32_t tv_hsize; + uint32_t tv_hdisp; + uint32_t tv_hstart; + uint32_t tv_vtotal; + uint32_t tv_vdisp; + uint32_t tv_timing_cntl; + uint32_t tv_vscaler_cntl1; + uint32_t tv_vscaler_cntl2; + uint32_t tv_sync_size; + uint32_t tv_vrestart; + uint32_t tv_hrestart; + uint32_t tv_frestart; + uint32_t tv_ftotal; + uint32_t tv_clock_sel_cntl; + uint32_t tv_clkout_cntl; + uint32_t tv_data_delay_a; + uint32_t tv_data_delay_b; + uint32_t tv_dac_cntl; + uint32_t tv_pll_cntl; + uint32_t tv_pll_cntl1; + uint32_t tv_pll_fine_cntl; + uint32_t tv_modulator_cntl1; + uint32_t tv_modulator_cntl2; + uint32_t tv_frame_lock_cntl; + uint32_t tv_pre_dac_mux_cntl; + uint32_t tv_rgb_cntl; + uint32_t tv_y_saw_tooth_cntl; + uint32_t tv_y_rise_cntl; + uint32_t tv_y_fall_cntl; + uint32_t tv_uv_adr; + uint32_t tv_upsamp_and_gain_cntl; + uint32_t tv_gain_limit_settings; + uint32_t tv_linear_gain_settings; + uint32_t tv_crc_cntl; + uint32_t tv_sync_cntl; + uint32_t gpiopad_a; + uint32_t pll_test_cntl; + + uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; + uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; } RADEONSaveRec, *RADEONSavePtr; diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 815bcaac..fb9f97fb 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -4466,7 +4466,7 @@ # define R300_ALU_RGB_ADDR0(x) (x << 0) # define R300_ALU_RGB_ADDR1(x) (x << 6) # define R300_ALU_RGB_ADDR2(x) (x << 12) -/* ADDRD - where on the pixle stack the result of this instruction +/* ADDRD - where on the pixel stack the result of this instruction will be written */ # define R300_ALU_RGB_ADDRD(x) (x << 18) # define R300_ALU_RGB_WMASK(x) (x << 23) @@ -4558,7 +4558,7 @@ # define R300_ALU_ALPHA_ADDR0(x) (x << 0) # define R300_ALU_ALPHA_ADDR1(x) (x << 6) # define R300_ALU_ALPHA_ADDR2(x) (x << 12) -/* ADDRD - where on the pixle stack the result of this instruction +/* ADDRD - where on the pixel stack the result of this instruction will be written */ # define R300_ALU_ALPHA_ADDRD(x) (x << 18) # define R300_ALU_ALPHA_WMASK(x) (x << 23) diff --git a/src/radeon_render.c b/src/radeon_render.c index 950753ca..b5661f96 100644 --- a/src/radeon_render.c +++ b/src/radeon_render.c @@ -46,7 +46,7 @@ struct blendinfo { Bool dst_alpha; Bool src_alpha; - CARD32 blend_cntl; + uint32_t blend_cntl; }; /* The first part of blend_cntl corresponds to Fa from the render "protocol" @@ -147,7 +147,7 @@ static const struct blendinfo RadeonBlendOp[] = { * The RADEON and R200 TXFORMATS we use are the same on r100/r200. */ -static CARD32 RADEONTextureFormats[] = { +static uint32_t RADEONTextureFormats[] = { PICT_a8r8g8b8, PICT_a8, PICT_x8r8g8b8, @@ -157,7 +157,7 @@ static CARD32 RADEONTextureFormats[] = { 0 }; -static CARD32 RADEONDstFormats[] = { +static uint32_t RADEONDstFormats[] = { PICT_a8r8g8b8, PICT_x8r8g8b8, PICT_r5g6b5, @@ -166,8 +166,8 @@ static CARD32 RADEONDstFormats[] = { 0 }; -static CARD32 -RadeonGetTextureFormat(CARD32 format) +static uint32_t +RadeonGetTextureFormat(uint32_t format) { switch (format) { case PICT_a8r8g8b8: @@ -187,8 +187,8 @@ RadeonGetTextureFormat(CARD32 format) } } -static CARD32 -RadeonGetColorFormat(CARD32 format) +static uint32_t +RadeonGetColorFormat(uint32_t format) { switch (format) { case PICT_a8r8g8b8: @@ -207,10 +207,10 @@ RadeonGetColorFormat(CARD32 format) /* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not * supported */ -static CARD32 -RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) +static uint32_t +RadeonGetBlendCntl(uint8_t op, uint32_t dstFormat) { - CARD32 blend_cntl; + uint32_t blend_cntl; if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0) return 0; @@ -218,7 +218,7 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) blend_cntl = RadeonBlendOp[op].blend_cntl; if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) { - CARD32 srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; + uint32_t srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; /* If there's no destination alpha channel, we need to wire the blending * to treat the alpha channel as always 1. @@ -235,11 +235,11 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) return blend_cntl; } -static __inline__ CARD32 F_TO_DW(float val) +static __inline__ uint32_t F_TO_DW(float val) { union { float f; - CARD32 l; + uint32_t l; } tmp; tmp.f = val; return tmp.l; @@ -324,7 +324,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 swapper = info->ModeReg->surface_cntl; + uint32_t swapper = info->ModeReg->surface_cntl; swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); @@ -380,22 +380,22 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info) static Bool FUNC_NAME(R100SetupTexture)( ScrnInfoPtr pScrn, - CARD32 format, - CARD8 *src, + uint32_t format, + uint8_t *src, int src_pitch, unsigned int width, unsigned int height, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD8 *dst; - CARD32 tex_size = 0, txformat; + uint8_t *dst; + uint32_t tex_size = 0, txformat; int dst_pitch, offset, size, tex_bytepp; #ifdef ACCEL_CP - CARD32 buf_pitch, dst_pitch_off; + uint32_t buf_pitch, dst_pitch_off; int x, y; unsigned int hpass; - CARD8 *tmp_dst; + uint8_t *tmp_dst; #endif ACCEL_PREAMBLE(); @@ -436,7 +436,7 @@ static Bool FUNC_NAME(R100SetupTexture)( } offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; - dst = (CARD8*)(info->FB + offset); + dst = (uint8_t*)(info->FB + offset); /* Upload texture to card. */ @@ -493,13 +493,13 @@ static Bool FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( ScrnInfoPtr pScrn, int op, - CARD16 red, - CARD16 green, - CARD16 blue, - CARD16 alpha, - CARD32 maskFormat, - CARD32 dstFormat, - CARD8 *alphaPtr, + uint16_t red, + uint16_t green, + uint16_t blue, + uint16_t alpha, + uint32_t maskFormat, + uint32_t dstFormat, + uint8_t *alphaPtr, int alphaPitch, int width, int height, @@ -507,7 +507,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( ) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 colorformat, srccolor, blend_cntl; + uint32_t colorformat, srccolor, blend_cntl; ACCEL_PREAMBLE(); blend_cntl = RadeonGetBlendCntl(op, dstFormat); @@ -548,9 +548,9 @@ static Bool FUNC_NAME(R100SetupForCPUToScreenTexture) ( ScrnInfoPtr pScrn, int op, - CARD32 srcFormat, - CARD32 dstFormat, - CARD8 *texPtr, + uint32_t srcFormat, + uint32_t dstFormat, + uint8_t *texPtr, int texPitch, int width, int height, @@ -558,7 +558,7 @@ FUNC_NAME(R100SetupForCPUToScreenTexture) ( ) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 colorformat, blend_cntl; + uint32_t colorformat, blend_cntl; ACCEL_PREAMBLE(); blend_cntl = RadeonGetBlendCntl(op, dstFormat); @@ -605,7 +605,7 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( { RADEONInfoPtr info = RADEONPTR(pScrn); int byteshift; - CARD32 fboffset; + uint32_t fboffset; float l, t, r, b, fl, fr, ft, fb; ACCEL_PREAMBLE(); @@ -717,22 +717,22 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( static Bool FUNC_NAME(R200SetupTexture)( ScrnInfoPtr pScrn, - CARD32 format, - CARD8 *src, + uint32_t format, + uint8_t *src, int src_pitch, unsigned int width, unsigned int height, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD8 *dst; - CARD32 tex_size = 0, txformat; + uint8_t *dst; + uint32_t tex_size = 0, txformat; int dst_pitch, offset, size, tex_bytepp; #ifdef ACCEL_CP - CARD32 buf_pitch, dst_pitch_off; + uint32_t buf_pitch, dst_pitch_off; int x, y; unsigned int hpass; - CARD8 *tmp_dst; + uint8_t *tmp_dst; #endif ACCEL_PREAMBLE(); @@ -776,7 +776,7 @@ static Bool FUNC_NAME(R200SetupTexture)( info->texH[0] = height; offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; - dst = (CARD8*)(info->FB + offset); + dst = (uint8_t*)(info->FB + offset); /* Upload texture to card. */ @@ -834,13 +834,13 @@ static Bool FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( ScrnInfoPtr pScrn, int op, - CARD16 red, - CARD16 green, - CARD16 blue, - CARD16 alpha, - CARD32 maskFormat, - CARD32 dstFormat, - CARD8 *alphaPtr, + uint16_t red, + uint16_t green, + uint16_t blue, + uint16_t alpha, + uint32_t maskFormat, + uint32_t dstFormat, + uint8_t *alphaPtr, int alphaPitch, int width, int height, @@ -848,7 +848,7 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( ) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 colorformat, srccolor, blend_cntl; + uint32_t colorformat, srccolor, blend_cntl; ACCEL_PREAMBLE(); blend_cntl = RadeonGetBlendCntl(op, dstFormat); @@ -890,9 +890,9 @@ static Bool FUNC_NAME(R200SetupForCPUToScreenTexture) ( ScrnInfoPtr pScrn, int op, - CARD32 srcFormat, - CARD32 dstFormat, - CARD8 *texPtr, + uint32_t srcFormat, + uint32_t dstFormat, + uint8_t *texPtr, int texPitch, int width, int height, @@ -900,7 +900,7 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) ( ) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 colorformat, blend_cntl; + uint32_t colorformat, blend_cntl; ACCEL_PREAMBLE(); blend_cntl = RadeonGetBlendCntl(op, dstFormat); @@ -948,7 +948,7 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) ( { RADEONInfoPtr info = RADEONPTR(pScrn); int byteshift; - CARD32 fboffset; + uint32_t fboffset; float l, t, r, b, fl, fr, ft, fb; ACCEL_PREAMBLE(); diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c index 5d153e74..cfa349d3 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -70,11 +70,11 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) } } -static __inline__ CARD32 F_TO_DW(float val) +static __inline__ uint32_t F_TO_DW(float val) { union { float f; - CARD32 l; + uint32_t l; } tmp; tmp.f = val; return tmp.l; @@ -227,7 +227,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; pPriv->src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset; - pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch)); + pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); pPriv->src_pitch = dstPitch; pPriv->size = size; pPriv->pDraw = pDraw; diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index b0286a6d..d5d1b1cf 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -74,11 +74,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; - CARD32 txformat; - CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; - CARD32 dst_offset, dst_pitch, dst_format; - CARD32 txenable, colorpitch; - CARD32 blendcntl; + uint32_t txformat; + uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; + uint32_t dst_offset, dst_pitch, dst_format; + uint32_t txenable, colorpitch; + uint32_t blendcntl; int dstxoff, dstyoff, pixel_shift; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); @@ -121,7 +121,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv FINISH_VIDEO(); if (IS_R300_3D || IS_R500_3D) { - CARD32 output_fmt; + uint32_t output_fmt; switch (pPixmap->drawable.bitsPerPixel) { case 16: diff --git a/src/radeon_tv.c b/src/radeon_tv.c index d5d1e9e7..90020b31 100644 --- a/src/radeon_tv.c +++ b/src/radeon_tv.c @@ -34,22 +34,22 @@ typedef struct { - CARD16 horResolution; - CARD16 verResolution; + uint16_t horResolution; + uint16_t verResolution; TVStd standard; - CARD16 horTotal; - CARD16 verTotal; - CARD16 horStart; - CARD16 horSyncStart; - CARD16 verSyncStart; + uint16_t horTotal; + uint16_t verTotal; + uint16_t horStart; + uint16_t horSyncStart; + uint16_t verSyncStart; unsigned defRestart; - CARD16 crtcPLL_N; - CARD8 crtcPLL_M; - CARD8 crtcPLL_postDiv; + uint16_t crtcPLL_N; + uint8_t crtcPLL_M; + uint8_t crtcPLL_postDiv; unsigned pixToTV; } TVModeConstants; -static const CARD16 hor_timing_NTSC[] = +static const uint16_t hor_timing_NTSC[] = { 0x0007, 0x003f, @@ -71,7 +71,7 @@ static const CARD16 hor_timing_NTSC[] = 0 }; -static const CARD16 vert_timing_NTSC[] = +static const uint16_t vert_timing_NTSC[] = { 0x2001, 0x200d, @@ -89,7 +89,7 @@ static const CARD16 vert_timing_NTSC[] = 0 }; -static const CARD16 hor_timing_PAL[] = +static const uint16_t hor_timing_PAL[] = { 0x0007, 0x0058, @@ -111,7 +111,7 @@ static const CARD16 hor_timing_PAL[] = 0 }; -static const CARD16 vert_timing_PAL[] = +static const uint16_t vert_timing_PAL[] = { 0x2001, 0x200c, @@ -186,7 +186,7 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 savePLLTest; + uint32_t savePLLTest; unsigned i; unsigned j; @@ -215,12 +215,12 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, /* Write to TV FIFO RAM */ static void -RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, - CARD32 value) +RADEONWriteTVFIFO(ScrnInfoPtr pScrn, uint16_t addr, + uint32_t value) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; + uint32_t tmp; int i = 0; OUTREG(RADEON_TV_HOST_WRITE_DATA, value); @@ -241,12 +241,12 @@ RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, } /* Read from TV FIFO RAM */ -static CARD32 -RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) +static uint32_t +RADEONReadTVFIFO(ScrnInfoPtr pScrn, uint16_t addr) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; + uint32_t tmp; int i = 0; OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr); @@ -269,10 +269,10 @@ RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) /* Get FIFO addresses of horizontal & vertical code timing tables from * settings of uv_adr register. */ -static CARD16 -RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) +static uint16_t +RADEONGetHTimingTablesAddr(uint32_t tv_uv_adr) { - CARD16 hTable; + uint16_t hTable; switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { case 0: @@ -292,10 +292,10 @@ RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) return hTable; } -static CARD16 -RADEONGetVTimingTablesAddr(CARD32 tv_uv_adr) +static uint16_t +RADEONGetVTimingTablesAddr(uint32_t tv_uv_adr) { - CARD16 vTable; + uint16_t vTable; switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { case 0: @@ -321,9 +321,9 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD16 hTable; - CARD16 vTable; - CARD32 tmp; + uint16_t hTable; + uint16_t vTable; + uint32_t tmp; unsigned i; OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr); @@ -331,14 +331,14 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr); for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) { - tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]); + tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]); RADEONWriteTVFIFO(pScrn, hTable, tmp); if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0) break; } for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, vTable++) { - tmp = ((CARD32)restore->v_code_timing[ i + 1 ] << 14) | ((CARD32)restore->v_code_timing[ i ]); + tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore->v_code_timing[ i ]); RADEONWriteTVFIFO(pScrn, vTable, tmp); if (restore->v_code_timing[ i ] == 0 || restore->v_code_timing[ i + 1 ] == 0) break; @@ -485,9 +485,9 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD16 hTable; - CARD16 vTable; - CARD32 tmp; + uint16_t hTable; + uint16_t vTable; + uint32_t tmp; unsigned i; save->tv_uv_adr = INREG(RADEON_TV_UV_ADR); @@ -511,8 +511,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2) { tmp = RADEONReadTVFIFO(pScrn, hTable--); - save->h_code_timing[ i ] = (CARD16)((tmp >> 14) & 0x3fff); - save->h_code_timing[ i + 1 ] = (CARD16)(tmp & 0x3fff); + save->h_code_timing[ i ] = (uint16_t)((tmp >> 14) & 0x3fff); + save->h_code_timing[ i + 1 ] = (uint16_t)(tmp & 0x3fff); if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0) break; @@ -520,8 +520,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2) { tmp = RADEONReadTVFIFO(pScrn, vTable++); - save->v_code_timing[ i ] = (CARD16)(tmp & 0x3fff); - save->v_code_timing[ i + 1 ] = (CARD16)((tmp >> 14) & 0x3fff); + save->v_code_timing[ i ] = (uint16_t)(tmp & 0x3fff); + save->v_code_timing[ i + 1 ] = (uint16_t)((tmp >> 14) & 0x3fff); if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0) break; @@ -588,10 +588,10 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, unsigned fTotal; int vOffset; int hOffset; - CARD16 p1; - CARD16 p2; + uint16_t p1; + uint16_t p2; Bool hChanged; - CARD16 hInc; + uint16_t hInc; const TVModeConstants *constPtr; /* FIXME: need to revisit this when we add more modes */ @@ -629,8 +629,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, } - p1 = (CARD16)((int)p1 + hOffset); - p2 = (CARD16)((int)p2 - hOffset); + p1 = (uint16_t)((int)p1 + hOffset); + p2 = (uint16_t)((int)p2 - hOffset); hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] || p2 != save->h_code_timing[ H_TABLE_POS2 ]); @@ -675,14 +675,14 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, if (radeon_output->tvStd == TV_STD_NTSC || radeon_output->tvStd == TV_STD_NTSC_J || radeon_output->tvStd == TV_STD_PAL_M) - hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / + hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / (radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); else - hInc = (CARD16)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / + hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / (radeon_output->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) | - ((CARD32)hInc << RADEON_H_INC_SHIFT); + ((uint32_t)hInc << RADEON_H_INC_SHIFT); ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , radeon_output->hSize , hInc); @@ -698,10 +698,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, RADEONInfoPtr info = RADEONPTR(pScrn); unsigned i; unsigned long vert_space, flicker_removal; - CARD32 tmp; + uint32_t tmp; const TVModeConstants *constPtr; - const CARD16 *hor_timing; - const CARD16 *vert_timing; + const uint16_t *hor_timing; + const uint16_t *vert_timing; /* FIXME: need to revisit this when we add more modes */ diff --git a/src/radeon_video.c b/src/radeon_video.c index 4cd35134..d4b9ac4f 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -558,59 +558,59 @@ static REF_TRANSFORM trans[2] = /* Gamma curve definition for preset gammas */ typedef struct tagGAMMA_CURVE_R100 { - CARD32 GAMMA_0_F_SLOPE; - CARD32 GAMMA_0_F_OFFSET; - CARD32 GAMMA_10_1F_SLOPE; - CARD32 GAMMA_10_1F_OFFSET; - CARD32 GAMMA_20_3F_SLOPE; - CARD32 GAMMA_20_3F_OFFSET; - CARD32 GAMMA_40_7F_SLOPE; - CARD32 GAMMA_40_7F_OFFSET; - CARD32 GAMMA_380_3BF_SLOPE; - CARD32 GAMMA_380_3BF_OFFSET; - CARD32 GAMMA_3C0_3FF_SLOPE; - CARD32 GAMMA_3C0_3FF_OFFSET; + uint32_t GAMMA_0_F_SLOPE; + uint32_t GAMMA_0_F_OFFSET; + uint32_t GAMMA_10_1F_SLOPE; + uint32_t GAMMA_10_1F_OFFSET; + uint32_t GAMMA_20_3F_SLOPE; + uint32_t GAMMA_20_3F_OFFSET; + uint32_t GAMMA_40_7F_SLOPE; + uint32_t GAMMA_40_7F_OFFSET; + uint32_t GAMMA_380_3BF_SLOPE; + uint32_t GAMMA_380_3BF_OFFSET; + uint32_t GAMMA_3C0_3FF_SLOPE; + uint32_t GAMMA_3C0_3FF_OFFSET; float OvGammaCont; } GAMMA_CURVE_R100; typedef struct tagGAMMA_CURVE_R200 { - CARD32 GAMMA_0_F_SLOPE; - CARD32 GAMMA_0_F_OFFSET; - CARD32 GAMMA_10_1F_SLOPE; - CARD32 GAMMA_10_1F_OFFSET; - CARD32 GAMMA_20_3F_SLOPE; - CARD32 GAMMA_20_3F_OFFSET; - CARD32 GAMMA_40_7F_SLOPE; - CARD32 GAMMA_40_7F_OFFSET; - CARD32 GAMMA_80_BF_SLOPE; - CARD32 GAMMA_80_BF_OFFSET; - CARD32 GAMMA_C0_FF_SLOPE; - CARD32 GAMMA_C0_FF_OFFSET; - CARD32 GAMMA_100_13F_SLOPE; - CARD32 GAMMA_100_13F_OFFSET; - CARD32 GAMMA_140_17F_SLOPE; - CARD32 GAMMA_140_17F_OFFSET; - CARD32 GAMMA_180_1BF_SLOPE; - CARD32 GAMMA_180_1BF_OFFSET; - CARD32 GAMMA_1C0_1FF_SLOPE; - CARD32 GAMMA_1C0_1FF_OFFSET; - CARD32 GAMMA_200_23F_SLOPE; - CARD32 GAMMA_200_23F_OFFSET; - CARD32 GAMMA_240_27F_SLOPE; - CARD32 GAMMA_240_27F_OFFSET; - CARD32 GAMMA_280_2BF_SLOPE; - CARD32 GAMMA_280_2BF_OFFSET; - CARD32 GAMMA_2C0_2FF_SLOPE; - CARD32 GAMMA_2C0_2FF_OFFSET; - CARD32 GAMMA_300_33F_SLOPE; - CARD32 GAMMA_300_33F_OFFSET; - CARD32 GAMMA_340_37F_SLOPE; - CARD32 GAMMA_340_37F_OFFSET; - CARD32 GAMMA_380_3BF_SLOPE; - CARD32 GAMMA_380_3BF_OFFSET; - CARD32 GAMMA_3C0_3FF_SLOPE; - CARD32 GAMMA_3C0_3FF_OFFSET; + uint32_t GAMMA_0_F_SLOPE; + uint32_t GAMMA_0_F_OFFSET; + uint32_t GAMMA_10_1F_SLOPE; + uint32_t GAMMA_10_1F_OFFSET; + uint32_t GAMMA_20_3F_SLOPE; + uint32_t GAMMA_20_3F_OFFSET; + uint32_t GAMMA_40_7F_SLOPE; + uint32_t GAMMA_40_7F_OFFSET; + uint32_t GAMMA_80_BF_SLOPE; + uint32_t GAMMA_80_BF_OFFSET; + uint32_t GAMMA_C0_FF_SLOPE; + uint32_t GAMMA_C0_FF_OFFSET; + uint32_t GAMMA_100_13F_SLOPE; + uint32_t GAMMA_100_13F_OFFSET; + uint32_t GAMMA_140_17F_SLOPE; + uint32_t GAMMA_140_17F_OFFSET; + uint32_t GAMMA_180_1BF_SLOPE; + uint32_t GAMMA_180_1BF_OFFSET; + uint32_t GAMMA_1C0_1FF_SLOPE; + uint32_t GAMMA_1C0_1FF_OFFSET; + uint32_t GAMMA_200_23F_SLOPE; + uint32_t GAMMA_200_23F_OFFSET; + uint32_t GAMMA_240_27F_SLOPE; + uint32_t GAMMA_240_27F_OFFSET; + uint32_t GAMMA_280_2BF_SLOPE; + uint32_t GAMMA_280_2BF_OFFSET; + uint32_t GAMMA_2C0_2FF_SLOPE; + uint32_t GAMMA_2C0_2FF_OFFSET; + uint32_t GAMMA_300_33F_SLOPE; + uint32_t GAMMA_300_33F_OFFSET; + uint32_t GAMMA_340_37F_SLOPE; + uint32_t GAMMA_340_37F_OFFSET; + uint32_t GAMMA_380_3BF_SLOPE; + uint32_t GAMMA_380_3BF_OFFSET; + uint32_t GAMMA_3C0_3FF_SLOPE; + uint32_t GAMMA_3C0_3FF_OFFSET; float OvGammaCont; } GAMMA_CURVE_R200; @@ -849,11 +849,11 @@ static GAMMA_CURVE_R200 gamma_curve_r200[8] = }; static void -RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma) +RADEONSetOverlayGamma(ScrnInfoPtr pScrn, uint32_t gamma) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 ov0_scale_cntl; + uint32_t ov0_scale_cntl; /* Set gamma */ RADEONWaitForIdleMMIO(pScrn); @@ -965,8 +965,8 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, float red_intensity, float green_intensity, float blue_intensity, - CARD32 ref, - CARD32 user_gamma) + uint32_t ref, + uint32_t user_gamma) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -983,11 +983,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, float Loff = 64.0; float Coff = 512.0f; - CARD32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; - CARD32 dwOvRCb, dwOvRCr; - CARD32 dwOvGCb, dwOvGCr; - CARD32 dwOvBCb, dwOvBCr; - CARD32 gamma = 0; + uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; + uint32_t dwOvRCb, dwOvRCr; + uint32_t dwOvGCb, dwOvGCr; + uint32_t dwOvBCb, dwOvBCr; + uint32_t gamma = 0; if (ref >= 2) return; @@ -1151,16 +1151,16 @@ static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, /* not yet supported */ } -static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) +static void RADEONSetColorKey(ScrnInfoPtr pScrn, uint32_t colorKey) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 min, max; - CARD8 r, g, b; + uint32_t min, max; + uint8_t r, g, b; if (info->CurrentLayout.depth > 8) { - CARD32 rbits, gbits, bbits; + uint32_t rbits, gbits, bbits; rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red; gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green; @@ -1172,7 +1172,7 @@ static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) } else { - CARD32 bits; + uint32_t bits; bits = colorKey & ((1 << info->CurrentLayout.depth) - 1); r = bits; @@ -1315,7 +1315,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) RADEONPLLPtr pll = &(info->pll); TheatrePtr t; - CARD8 a; + uint8_t a; int i; pPriv->theatre = NULL; @@ -1409,7 +1409,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) XF86VideoAdaptorPtr adapt; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv; - CARD32 dot_clock; + uint32_t dot_clock; int ecp; if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) @@ -2178,8 +2178,8 @@ RADEONCopyData( if ( info->directRenderingEnabled && info->DMAForXv ) { - CARD8 *buf; - CARD32 bufPitch, dstPitchOff; + uint8_t *buf; + uint32_t bufPitch, dstPitchOff; int x, y; unsigned int hpass; @@ -2243,21 +2243,21 @@ RADEONCopyRGB24Data( unsigned int h, unsigned int w ){ - CARD32 *dptr; - CARD8 *sptr; + uint32_t *dptr; + uint8_t *sptr; int i,j; RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86DRI if ( info->directRenderingEnabled && info->DMAForXv ) { - CARD32 bufPitch, dstPitchOff; + uint32_t bufPitch, dstPitchOff; int x, y; unsigned int hpass; RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); - while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, + while ( (dptr = ( uint32_t* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, &bufPitch, x, &y, &h, &hpass )) ) { @@ -2290,7 +2290,7 @@ RADEONCopyRGB24Data( #endif for (j = 0; j < h; j++) { - dptr = (CARD32 *)(dst + j * dstPitch); + dptr = (uint32_t *)(dst + j * dstPitch); sptr = src + j * srcPitch; for (i = 0; i < w; i++, sptr += 3) { @@ -2341,8 +2341,8 @@ RADEONCopyMungedData( if ( info->directRenderingEnabled && info->DMAForXv ) { - CARD8 *buf; - CARD32 y = 0, bufPitch, dstPitchOff; + uint8_t *buf; + uint32_t y = 0, bufPitch, dstPitchOff; int blitX, blitY; unsigned int hpass; @@ -2373,8 +2373,8 @@ RADEONCopyMungedData( else #endif /* XF86DRI */ { - CARD32 *dst; - CARD8 *s1, *s2, *s3; + uint32_t *dst; + uint8_t *s1, *s2, *s3; int i, j; #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -2428,7 +2428,7 @@ RADEONCopyMungedData( * is measured in bytes, and the offset from the beginning of card space is * returned. */ -CARD32 +uint32_t RADEONAllocateMemory( ScrnInfoPtr pScrn, void **mem_struct, @@ -2550,7 +2550,7 @@ RADEONDisplayVideo( RADEONInfoPtr info = RADEONPTR(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; + uint32_t v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; double h_inc_d; int p1_h_accum_init, p23_h_accum_init; int p1_v_accum_init, p23_v_accum_init; @@ -2560,12 +2560,12 @@ RADEONDisplayVideo( int y_mult; int x_off; int y_off; - CARD32 scaler_src; - CARD32 dot_clock; + uint32_t scaler_src; + uint32_t dot_clock; int is_rgb; int is_planar; int i; - CARD32 scale_cntl; + uint32_t scale_cntl; double dsr; int tap_set; int predownscale=0; @@ -2881,7 +2881,7 @@ RADEONDisplayVideo( static void -RADEONFillKeyHelper(DrawablePtr pDraw, CARD32 colorKey, RegionPtr clipBoxes) +RADEONFillKeyHelper(DrawablePtr pDraw, uint32_t colorKey, RegionPtr clipBoxes) { #if HAVE_XV_DRAWABLE_HELPER xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes); @@ -2914,7 +2914,7 @@ RADEONPutImage( int top, left, npixels, nlines, bpp; int idconv = id; BoxRec dstBox; - CARD32 tmp; + uint32_t tmp; xf86CrtcPtr crtc; /* @@ -3470,7 +3470,7 @@ RADEONPutVideo( int srcPitch, srcPitch2, dstPitch; int bpp; BoxRec dstBox; - CARD32 id, display_base; + uint32_t id, display_base; int width, height; int mult; int vbi_line_width, vbi_start, vbi_end; diff --git a/src/radeon_video.h b/src/radeon_video.h index f897e073..096de372 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h @@ -15,8 +15,8 @@ /* Xvideo port struct */ typedef struct { - CARD32 transform_index; - CARD32 gamma; /* gamma value x 1000 */ + uint32_t transform_index; + uint32_t gamma; /* gamma value x 1000 */ int brightness; int saturation; int hue; @@ -32,17 +32,17 @@ typedef struct { /* i2c bus and devices */ I2CBusPtr i2c; - CARD32 radeon_i2c_timing; - CARD32 radeon_M; - CARD32 radeon_N; - CARD32 i2c_status; - CARD32 i2c_cntl; + uint32_t radeon_i2c_timing; + uint32_t radeon_M; + uint32_t radeon_N; + uint32_t i2c_status; + uint32_t i2c_cntl; FI1236Ptr fi1236; - CARD8 tuner_type; + uint8_t tuner_type; MSP3430Ptr msp3430; TDA9885Ptr tda9885; - UDA1380Ptr uda1380; + UDA1380Ptr uda1380; /* VIP bus and devices */ GENERIC_BUS_Ptr VIP; @@ -50,12 +50,12 @@ typedef struct { Bool video_stream_active; int encoding; - CARD32 frequency; + uint32_t frequency; int volume; Bool mute; int sap_channel; int v; - CARD32 adjustment; /* general purpose variable */ + uint32_t adjustment; /* general purpose variable */ #define METHOD_BOB 0 #define METHOD_SINGLE 1 @@ -74,14 +74,14 @@ typedef struct { Bool doubleBuffer; unsigned char currentBuffer; RegionRec clip; - CARD32 colorKey; - CARD32 videoStatus; + uint32_t colorKey; + uint32_t videoStatus; Time offTime; Time freeTime; Bool autopaint_colorkey; xf86CrtcPtr desired_crtc; - int size; + int size; #ifdef USE_EXA ExaOffscreenArea *off_screen; #endif @@ -96,9 +96,9 @@ typedef struct { DrawablePtr pDraw; PixmapPtr pPixmap; - CARD32 src_offset; - CARD32 src_pitch; - CARD8 *src_addr; + uint32_t src_offset; + uint32_t src_pitch; + uint8_t *src_addr; int id; int src_w, src_h, dst_w, dst_h; @@ -113,7 +113,7 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -CARD32 +uint32_t RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size); void RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct); diff --git a/src/radeon_vip.c b/src/radeon_vip.c index 7ee4ab5b..05b90f19 100644 --- a/src/radeon_vip.c +++ b/src/radeon_vip.c @@ -46,13 +46,13 @@ static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2 } } -static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) +static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 timeout; + uint32_t timeout; RADEONWaitForIdleMMIO(pScrn); timeout = INREG(RADEON_VIPH_TIMEOUT_STAT); @@ -67,13 +67,13 @@ static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ; } -static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) +static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 timeout; + uint32_t timeout; RADEONWaitForIdleMMIO(pScrn); timeout = INREG(VIPH_TIMEOUT_STAT); @@ -105,12 +105,12 @@ static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) } \ } -static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) +static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 status,tmp; + uint32_t status,tmp; if((count!=1) && (count!=2) && (count!=4)) { @@ -152,13 +152,13 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD RADEONWaitForIdleMMIO(pScrn); switch(count){ case 1: - *buffer=(CARD8)(INREG(RADEON_VIPH_REG_DATA) & 0xff); + *buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff); break; case 2: - *(CARD16 *)buffer=(CARD16) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); + *(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); break; case 4: - *(CARD32 *)buffer=(CARD32) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); + *(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); break; } VIP_WAIT_FOR_IDLE(); @@ -171,12 +171,12 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD return TRUE; } -static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) +static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 status,tmp; + uint32_t status,tmp; if(count!=1) { @@ -222,13 +222,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, RADEONWaitForIdleMMIO(pScrn); switch(count){ case 1: - *buffer=(CARD8)(INREG(VIPH_REG_DATA) & 0xff); + *buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff); break; case 2: - *(CARD16 *)buffer=(CARD16) (INREG(VIPH_REG_DATA) & 0xffff); + *(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff); break; case 4: - *(CARD32 *)buffer=(CARD32) ( INREG(VIPH_REG_DATA) & 0xffffffff); + *(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff); break; } while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); @@ -245,13 +245,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, } -static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) +static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 status; + uint32_t status; if((count!=4)) @@ -269,7 +269,7 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR RADEONWaitForFifo(pScrn, 2); switch(count){ case 4: - OUTREG(RADEON_VIPH_REG_DATA, *(CARD32 *)buffer); + OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer); break; } write_mem_barrier(); @@ -278,14 +278,14 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR return TRUE; } -static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) +static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 status; - CARD32 i; + uint32_t status; + uint32_t i; RADEONWaitForFifo(pScrn, 2); OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000); @@ -300,7 +300,7 @@ static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count RADEONWaitForFifo(pScrn, 2); for (i = 0; i < count; i+=4) { - OUTREG(VIPH_REG_DATA, *(CARD32*)(buffer + i)); + OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i)); write_mem_barrier(); while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f))); if(VIP_IDLE != status) diff --git a/src/theatre.c b/src/theatre.c index a4d3c10d..ad055c5a 100644 --- a/src/theatre.c +++ b/src/theatre.c @@ -12,31 +12,31 @@ #undef write #undef ioctl -static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) +static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) { if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); + return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); } -static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) +static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) { if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); + return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); } #define RT_regr(reg,data) theatre_read(t,(reg),(data)) #define RT_regw(reg,data) theatre_write(t,(reg),(data)) #define VIP_TYPE "ATI VIP BUS" -static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard); -static void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector); +static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard); +static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector); #if 0 TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) { TheatrePtr t; - CARD32 i; - CARD32 val; + uint32_t i; + uint32_t val; char s[20]; b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); @@ -51,10 +51,10 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) t->theatre_num = -1; t->mode=MODE_UNINITIALIZED; - b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); + b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); for(i=0;i<4;i++) { - if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) + if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) { if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val); if(t->theatre_num>=0)continue; /* already found one instance */ @@ -173,7 +173,7 @@ fld_V_INT_LENGTH, fld_CRDR_ACTIVE_GAIN, fld_CBDB_ACTIVE_GAIN, fld_DVS_DIRECTION, -fld_DVS_VBI_CARD8_SWAP, +fld_DVS_VBI_UINT8_SWAP, fld_DVS_CLK_SELECT, fld_CONTINUOUS_STREAM, fld_DVSOUT_CLK_DRV, @@ -255,17 +255,17 @@ regRT_MAX_REGS typedef struct { - CARD8 size; - CARD32 fld_id; - CARD32 dwRegAddrLSBs; - CARD32 dwFldOffsetLSBs; - CARD32 dwMaskLSBs; - CARD32 addr2; - CARD32 offs2; - CARD32 mask2; - CARD32 dwCurrValue; - CARD32 rw; - } RTREGMAP; + uint8_t size; + uint32_t fld_id; + uint32_t dwRegAddrLSBs; + uint32_t dwFldOffsetLSBs; + uint32_t dwMaskLSBs; + uint32_t addr2; + uint32_t offs2; + uint32_t mask2; + uint32_t dwCurrValue; + uint32_t rw; +} RTREGMAP; #define READONLY 1 #define WRITEONLY 2 @@ -352,7 +352,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, -{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, +{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, @@ -431,7 +431,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ }; /* Rage Theatre's register fields default values: */ -CARD32 RT_RegDef[regRT_MAX_REGS]= +uint32_t RT_RegDef[regRT_MAX_REGS]= { fld_tmpReg1_def, fld_tmpReg2_def, @@ -509,7 +509,7 @@ fld_V_INT_LENGTH_def, fld_CRDR_ACTIVE_GAIN_def, fld_CBDB_ACTIVE_GAIN_def, fld_DVS_DIRECTION_def, -fld_DVS_VBI_CARD8_SWAP_def, +fld_DVS_VBI_UINT8_SWAP_def, fld_DVS_CLK_SELECT_def, fld_CONTINUOUS_STREAM_def, fld_DVSOUT_CLK_DRV_def, @@ -588,16 +588,16 @@ fld_GPIO_6_OUT_def, }; /**************************************************************************** - * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * + * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * * Function: Writes a register field within Rage Theatre * - * Inputs: CARD32 dwReg = register field to be written * - * CARD32 dwData = data that will be written to the reg field * + * Inputs: uint32_t dwReg = register field to be written * + * uint32_t dwData = data that will be written to the reg field * * Outputs: NONE * ****************************************************************************/ -static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) +static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) { - CARD32 dwResult=0; - CARD32 dwValue=0; + uint32_t dwResult=0; + uint32_t dwValue=0; if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) { @@ -617,14 +617,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) } /* WriteRT_fld ()... */ /**************************************************************************** - * ReadRT_fld (CARD32 dwReg) * + * ReadRT_fld (uint32_t dwReg) * * Function: Reads a register field within Rage Theatre * - * Inputs: CARD32 dwReg = register field to be read * - * Outputs: CARD32 - value read from register field * + * Inputs: uint32_t dwReg = register field to be read * + * Outputs: uint32_t - value read from register field * ****************************************************************************/ -static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) +static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) { - CARD32 dwResult=0; + uint32_t dwResult=0; if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) { @@ -643,15 +643,15 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) #define ReadRT_fld(a) ReadRT_fld1(t,(a)) /**************************************************************************** - * RT_SetVINClock (CARD16 wStandard) * + * RT_SetVINClock (uint16_t wStandard) * * Function: to set the VIN clock for the selected standard * - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) +static void RT_SetVINClock(TheatrePtr t, uint16_t wStandard) { - CARD32 dwM0=0, dwN0=0, dwP=0; - CARD8 ref_freq; + uint32_t dwM0=0, dwN0=0, dwP=0; + uint8_t ref_freq; /* Determine the reference frequency first. This can be obtained from the MMTABLE.video_decoder_type field (bits 4:7) @@ -659,9 +659,9 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) 27 or 29.49 MHz. */ /* R128ReadBIOS(0x48, - (CARD8 *)&bios_header, sizeof(bios_header)); + (uint8_t *)&bios_header, sizeof(bios_header)); R128ReadBIOS(bios_header + 0x30, - (CARD8 *)&pll_info_block, sizeof(pll_info_block)); + (uint8_t *)&pll_info_block, sizeof(pll_info_block)); R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type)); */ @@ -797,7 +797,7 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) ****************************************************************************/ _X_EXPORT void RT_SetTint (TheatrePtr t, int hue) { - CARD32 nhue = 0; + uint32_t nhue = 0; t->iHue=hue; /* Scale hue value from -1000<->1000 to -180<->180 */ @@ -824,11 +824,11 @@ _X_EXPORT void RT_SetTint (TheatrePtr t, int hue) case (DEC_SECAM): if (hue >= 0) { - nhue = (CARD32) (256 * hue)/360; + nhue = (uint32_t) (256 * hue)/360; } else { - nhue = (CARD32) (256 * (hue + 360))/360; + nhue = (uint32_t) (256 * (hue + 360))/360; } break; @@ -850,7 +850,7 @@ _X_EXPORT void RT_SetTint (TheatrePtr t, int hue) ****************************************************************************/ _X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) { - CARD16 wSaturation_V, wSaturation_U; + uint16_t wSaturation_V, wSaturation_U; double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0; /* VALIDATE SATURATION LEVEL */ @@ -875,8 +875,8 @@ _X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard); - wSaturation_U = (CARD16) ((dbCrGain * dbSaturation * 128.0) + 0.5); - wSaturation_V = (CARD16) ((dbCbGain * dbSaturation * 128.0) + 0.5); + wSaturation_U = (uint16_t) ((dbCrGain * dbSaturation * 128.0) + 0.5); + wSaturation_V = (uint16_t) ((dbCbGain * dbSaturation * 128.0) + 0.5); /* SET SATURATION LEVEL */ WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U); @@ -902,7 +902,7 @@ _X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) double dbYgain=0; double dbBrightness=0; double dbSetup=0; - CARD16 wBrightness=0; + uint16_t wBrightness=0; /* VALIDATE BRIGHTNESS LEVEL */ if (Brightness < -1000) @@ -952,7 +952,7 @@ _X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) break; } - wBrightness = (CARD16) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); + wBrightness = (uint16_t) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness); @@ -964,12 +964,12 @@ _X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) /**************************************************************************** - * RT_SetSharpness (CARD16 wSharpness) * + * RT_SetSharpness (uint16_t wSharpness) * * Function: sets the sharpness level for the Rage Theatre video in * - * Inputs: CARD16 wSharpness - the sharpness value to be set. * + * Inputs: uint16_t wSharpness - the sharpness value to be set. * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) +_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) { switch (wSharpness) { @@ -999,7 +999,7 @@ _X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) { double dbSynctipRef0=0, dbContrast=0; double dbYgain=0; - CARD8 bTempContrast=0; + uint8_t bTempContrast=0; /* VALIDATE CONTRAST LEVEL */ if (Contrast < -1000) @@ -1037,9 +1037,9 @@ _X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) break; } - bTempContrast = (CARD8) ((dbContrast * dbYgain * 64) + 0.5); + bTempContrast = (uint8_t) ((dbContrast * dbYgain * 64) + 0.5); - WriteRT_fld (fld_LP_CONTRAST, (CARD32)bTempContrast); + WriteRT_fld (fld_LP_CONTRAST, (uint32_t)bTempContrast); /* Save value for future modification */ t->dbContrast = dbContrast; @@ -1049,23 +1049,23 @@ _X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) } /* RT_SetContrast ()... */ /**************************************************************************** - * RT_SetInterlace (CARD8 bInterlace) * + * RT_SetInterlace (uint8_t bInterlace) * * Function: to set the interlacing pattern for the Rage Theatre video in * - * Inputs: CARD8 bInterlace * + * Inputs: uint8_t bInterlace * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) +_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) { switch(bInterlace) { case (TRUE): /*DEC_INTERLACE */ WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - t->wInterlaced = (CARD16) RT_DECINTERLACED; + t->wInterlaced = (uint16_t) RT_DECINTERLACED; break; case (FALSE): /*DEC_NONINTERLACE */ WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); - t->wInterlaced = (CARD16) RT_DECNONINTERLACED; + t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; break; default: break; @@ -1077,16 +1077,16 @@ _X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) /**************************************************************************** * GetStandardConstants (double *LPeriod, double *FPeriod, * - * double *Fsamp, CARD16 wStandard) * + * double *Fsamp, uint16_t wStandard) * * Function: return timing values for a given standard * * Inputs: double *LPeriod - * double *FPeriod - * double *Fsamp - sampling frequency used for a given standard * - * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ static void GetStandardConstants (double *LPeriod, double *FPeriod, - double *Fsamp, CARD16 wStandard) + double *Fsamp, uint16_t wStandard) { *LPeriod = 0.0; *FPeriod = 0.0; @@ -1139,15 +1139,15 @@ static void GetStandardConstants (double *LPeriod, double *FPeriod, /**************************************************************************** - * RT_SetStandard (CARD16 wStandard) * + * RT_SetStandard (uint16_t wStandard) * * Function: to set the input standard for the Rage Theatre video in * - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) +_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) { double dbFsamp=0, dbLPeriod=0, dbFPeriod=0; - CARD16 wFrameTotal = 0; + uint16_t wFrameTotal = 0; double dbSPPeriod = 4.70; xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", @@ -1157,7 +1157,7 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) /* Get the constants for the given standard. */ GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); - wFrameTotal = (CARD16) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); + wFrameTotal = (uint16_t) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); /* Procedures before setting the standards: */ WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK); @@ -1209,10 +1209,10 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); - WriteRT_fld (fld_UV_INT_START, (CARD8)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); + WriteRT_fld (fld_UV_INT_START, (uint8_t)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_NTSCM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_NTSCM_VSYNC_INT_HOLD); + WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_NTSCM_VSYNC_INT_TRIGGER); + WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_NTSCM_VSYNC_INT_HOLD); switch (wStandard & 0xFF00) { @@ -1285,7 +1285,7 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START); WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END); - WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); + WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); @@ -1302,11 +1302,11 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */ -/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ - WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); +/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ + WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); + WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); + WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); break; case (DEC_SECAM): /*PAL GROUP*/ @@ -1345,7 +1345,7 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */ WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */ - WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); + WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); @@ -1360,11 +1360,11 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); + WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); + WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); -/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ - WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); +/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ + WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); break; default: @@ -1383,37 +1383,37 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) } /* Set the following values according to the formulas */ - WriteRT_fld (fld_HS_LINE_TOTAL, (CARD16)((dbLPeriod * dbFsamp / 2.0) +0.5)); + WriteRT_fld (fld_HS_LINE_TOTAL, (uint16_t)((dbLPeriod * dbFsamp / 2.0) +0.5)); /* According to Ivo PAL/SECAM needs different treatment */ switch(wStandard & 0x00FF) { case DEC_PAL: case DEC_SECAM: - WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.5 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.5 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); - WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(2.39 * dbSPPeriod * dbFsamp / 2.0)); - /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)RT_PAL_FIELD_IDLOCATION); */ + WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.5 * dbSPPeriod * dbFsamp/2.0)); + WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.5 * dbSPPeriod * dbFsamp/2.0)); + WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); + WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(2.39 * dbSPPeriod * dbFsamp / 2.0)); + /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)RT_PAL_FIELD_IDLOCATION); */ /* According to docs the following value will work right, though the resulting stream deviates slightly from CCIR..., in particular the value that was before will do nuts to VCRs in pause/rewind state. */ - WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); + WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); WriteRT_fld (fld_HS_PLL_SGAIN, 2); break; case DEC_NTSC: - WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.75 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.25 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); - WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(1.15 * dbSPPeriod * dbFsamp / 2.0)); - /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)fld_VS_FIELD_IDLOCATION_def);*/ + WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.75 * dbSPPeriod * dbFsamp/2.0)); + WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.25 * dbSPPeriod * dbFsamp/2.0)); + WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); + WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(1.15 * dbSPPeriod * dbFsamp / 2.0)); + /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)fld_VS_FIELD_IDLOCATION_def);*/ /* I think the default value was the same as the one here.. does not hurt to hardcode it */ - WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); + WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); } - WriteRT_fld (fld_VS_FRAME_TOTAL, (CARD16)(wFrameTotal) + 10); - WriteRT_fld (fld_BLACK_INT_START, (CARD8)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); - WriteRT_fld (fld_SYNC_TIP_START, (CARD16)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); + WriteRT_fld (fld_VS_FRAME_TOTAL, (uint16_t)(wFrameTotal) + 10); + WriteRT_fld (fld_BLACK_INT_START, (uint8_t)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); + WriteRT_fld (fld_SYNC_TIP_START, (uint16_t)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); return; @@ -1422,19 +1422,19 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) /**************************************************************************** - * RT_SetCombFilter (CARD16 wStandard, CARD16 wConnector) * + * RT_SetCombFilter (uint16_t wStandard, uint16_t wConnector) * * Function: sets the input comb filter based on the standard and * * connector being used (composite vs. svideo) * - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * - * CARD16 wConnector - COMPOSITE, SVIDEO * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * + * uint16_t wConnector - COMPOSITE, SVIDEO * * Outputs: NONE * ****************************************************************************/ -static void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) +static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector) { - CARD32 dwComb_Cntl0=0; - CARD32 dwComb_Cntl1=0; - CARD32 dwComb_Cntl2=0; - CARD32 dwComb_Line_Length=0; + uint32_t dwComb_Cntl0=0; + uint32_t dwComb_Cntl1=0; + uint32_t dwComb_Cntl2=0; + uint32_t dwComb_Line_Length=0; switch (wConnector) { @@ -1560,28 +1560,28 @@ static void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) /**************************************************************************** - * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * - * CARD8 fCC_On, CARD8 fVBICap_On) * + * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * + * uint8_t fCC_On, uint8_t fVBICap_On) * * Function: sets the output video size for the Rage Theatre video in * - * Inputs: CARD16 wHorzSize - width of output in pixels * - * CARD16 wVertSize - height of output in pixels (lines) * - * CARD8 fCC_On - enable CC output * - * CARD8 fVBI_Cap_On - enable VBI capture * + * Inputs: uint16_t wHorzSize - width of output in pixels * + * uint16_t wVertSize - height of output in pixels (lines) * + * uint8_t fCC_On - enable CC output * + * uint8_t fVBI_Cap_On - enable VBI capture * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) +_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) { - CARD32 dwHwinStart=0; - CARD32 dwHScaleRatio=0; - CARD32 dwHActiveLength=0; - CARD32 dwVwinStart=0; - CARD32 dwVScaleRatio=0; - CARD32 dwVActiveLength=0; - CARD32 dwTempRatio=0; - CARD32 dwEvenFieldOffset=0; - CARD32 dwOddFieldOffset=0; - CARD32 dwXin=0; - CARD32 dwYin=0; + uint32_t dwHwinStart=0; + uint32_t dwHScaleRatio=0; + uint32_t dwHActiveLength=0; + uint32_t dwVwinStart=0; + uint32_t dwVScaleRatio=0; + uint32_t dwVActiveLength=0; + uint32_t dwTempRatio=0; + uint32_t dwEvenFieldOffset=0; + uint32_t dwOddFieldOffset=0; + uint32_t dwXin=0; + uint32_t dwYin=0; if (fVBICap_On) { @@ -1628,21 +1628,21 @@ _X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVe dwHwinStart = RT_NTSCM_H_IN_START; dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/ dwXin = RT_NTSC_H_ACTIVE_SIZE; - dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ dwHActiveLength = wHorzSize; break; case (DEC_PAL): dwHwinStart = RT_PAL_H_IN_START; dwXin = RT_PAL_H_ACTIVE_SIZE; - dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ dwHActiveLength = wHorzSize; break; case (DEC_SECAM): dwHwinStart = RT_SECAM_H_IN_START; dwXin = RT_SECAM_H_ACTIVE_SIZE; - dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ dwHActiveLength = wHorzSize; break; @@ -1657,24 +1657,24 @@ _X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVe dwVwinStart = RT_NTSCM_V_IN_START; /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/ dwYin = RT_NTSCM_V_ACTIVE_SIZE; - dwTempRatio = (CARD32)((long) wVertSize / dwYin); - dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); + dwTempRatio = (uint32_t)((long) wVertSize / dwYin); + dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); dwVScaleRatio = dwVScaleRatio & 0x00000FFF; dwVActiveLength = wVertSize/2; break; case (DEC_PAL): dwVwinStart = RT_PAL_V_IN_START; dwYin = RT_PAL_V_ACTIVE_SIZE; - dwTempRatio = (CARD32)(wVertSize/dwYin); - dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); + dwTempRatio = (uint32_t)(wVertSize/dwYin); + dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); dwVScaleRatio = dwVScaleRatio & 0x00000FFF; dwVActiveLength = wVertSize/2; break; case (DEC_SECAM): dwVwinStart = RT_SECAM_V_IN_START; dwYin = RT_SECAM_V_ACTIVE_SIZE; - dwTempRatio = (CARD32) (wVertSize / dwYin); - dwVScaleRatio = (CARD32) ((long) wVertSize * 2048L / dwYin); + dwTempRatio = (uint32_t) (wVertSize / dwYin); + dwVScaleRatio = (uint32_t) ((long) wVertSize * 2048L / dwYin); dwVScaleRatio = dwVScaleRatio & 0x00000FFF; dwVActiveLength = wVertSize/2; break; @@ -1685,14 +1685,14 @@ _X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVe /*4. Set up offset based on if interlaced or not:*/ if (t->wInterlaced == RT_DECINTERLACED) { - dwEvenFieldOffset = (CARD32) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); + dwEvenFieldOffset = (uint32_t) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); dwOddFieldOffset = dwEvenFieldOffset; WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); } else { - dwEvenFieldOffset = (CARD32)(dwTempRatio * 512.0); - dwOddFieldOffset = (CARD32)(2048 - dwEvenFieldOffset); + dwEvenFieldOffset = (uint32_t)(dwTempRatio * 512.0); + dwOddFieldOffset = (uint32_t)(2048 - dwEvenFieldOffset); WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0); } @@ -1718,14 +1718,14 @@ _X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVe /**************************************************************************** - * CalculateCrCbGain (double *CrGain, double *CbGain, CARD16 wStandard) * + * CalculateCrCbGain (double *CrGain, double *CbGain, uint16_t wStandard) * * Function: * * Inputs: double *CrGain - * double *CbGain - - * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard) +static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard) { #define UVFLTGAIN 1.5 #define FRMAX 280000.0 @@ -1775,15 +1775,15 @@ static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CAR /**************************************************************************** - * RT_SetConnector (CARD16 wStandard, int tunerFlag) * + * RT_SetConnector (uint16_t wStandard, int tunerFlag) * * Function: - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * int tunerFlag * Outputs: NONE * ****************************************************************************/ -void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) +void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) { - CARD32 dwTempContrast=0; + uint32_t dwTempContrast=0; int i; long counter; @@ -1868,7 +1868,7 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) _X_EXPORT void InitTheatre(TheatrePtr t) { - CARD32 data; + uint32_t data; /* 0 reset Rage Theatre */ @@ -1943,7 +1943,7 @@ _X_EXPORT void ShutdownTheatre(TheatrePtr t) _X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) { int i; - CARD32 data; + uint32_t data; for(i=0;i<0x900;i+=4) { @@ -1957,7 +1957,7 @@ _X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) void DumpRageTheatreRegsByName(TheatrePtr t) { int i; - CARD32 data; + uint32_t data; struct { char *name; long addr; } rt_reg_list[]={ { "ADC_CNTL ", 0x0400 }, { "ADC_DEBUG ", 0x0404 }, diff --git a/src/theatre.h b/src/theatre.h index 36d6e056..c70a0e02 100644 --- a/src/theatre.h +++ b/src/theatre.h @@ -8,30 +8,30 @@ typedef struct { GENERIC_BUS_Ptr VIP; - int theatre_num; - CARD32 theatre_id; - int mode; - char* microc_path; - char* microc_type; + int theatre_num; + uint32_t theatre_id; + int mode; + char* microc_path; + char* microc_type; - CARD16 video_decoder_type; - CARD32 wStandard; - CARD32 wConnector; - int iHue; - int iSaturation; - CARD32 wSaturation_U; - CARD32 wSaturation_V; - int iBrightness; - int dbBrightnessRatio; - CARD32 wSharpness; - int iContrast; - int dbContrast; - CARD32 wInterlaced; - CARD32 wTunerConnector; - CARD32 wComp0Connector; - CARD32 wSVideo0Connector; - CARD32 dwHorzScalingRatio; - CARD32 dwVertScalingRatio; + uint16_t video_decoder_type; + uint32_t wStandard; + uint32_t wConnector; + int iHue; + int iSaturation; + uint32_t wSaturation_U; + uint32_t wSaturation_V; + int iBrightness; + int dbBrightnessRatio; + uint32_t wSharpness; + int iContrast; + int dbContrast; + uint32_t wInterlaced; + uint32_t wTunerConnector; + uint32_t wComp0Connector; + uint32_t wSVideo0Connector; + uint32_t dwHorzScalingRatio; + uint32_t dwVertScalingRatio; } TheatreRec, * TheatrePtr; @@ -46,17 +46,17 @@ _X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation); #define xf86_RT_SetBrightness RT_SetBrightness _X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness); #define xf86_RT_SetSharpness RT_SetSharpness -_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness); +_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness); #define xf86_RT_SetContrast RT_SetContrast _X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast); #define xf86_RT_SetInterlace RT_SetInterlace -_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace); +_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace); #define xf86_RT_SetStandard RT_SetStandard -_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard); +_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard); #define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On); +_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On); #define xf86_RT_SetConnector RT_SetConnector -_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag); +_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag); #define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout _X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t); #define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout diff --git a/src/theatre200.c b/src/theatre200.c index 0341c6e9..c150ed4e 100644 --- a/src/theatre200.c +++ b/src/theatre200.c @@ -71,51 +71,51 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen); static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); -static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0); -static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector); -//static CARD32 dsp_reset(TheatrePtr t); -static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate); -static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard); -static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format); -static CARD32 dsp_video_standard_detection(TheatrePtr t); -//static CARD32 dsp_get_signallockstatus(TheatrePtr t); -//static CARD32 dsp_get_signallinenumber(TheatrePtr t); - -static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness); -static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast); -//static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness); -static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint); -static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation); -static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end); -static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end); -static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right); -static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute); -//static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option); -static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode); -static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state); - -static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) +static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); +static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); +//static uint32_t dsp_reset(TheatrePtr t); +static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); +static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); +static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); +static uint32_t dsp_video_standard_detection(TheatrePtr t); +//static uint32_t dsp_get_signallockstatus(TheatrePtr t); +//static uint32_t dsp_get_signallinenumber(TheatrePtr t); + +static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); +static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); +//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); +static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); +static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); +static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); +static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); +static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); +static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); +//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); +static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); +static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); + +static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) { if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); + return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); } -static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) +static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) { if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); + return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); } -static Bool theatre_fifo_read(TheatrePtr t,CARD32 fifo, CARD8 *data) +static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) { if(t->theatre_num<0)return FALSE; - return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (CARD8 *) data); + return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); } -static Bool theatre_fifo_write(TheatrePtr t,CARD32 fifo, CARD32 count, CARD8* buffer) +static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) { if(t->theatre_num<0)return FALSE; - return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (CARD8 *)buffer); + return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); } #define RT_regr(reg,data) theatre_read(t,(reg),(data)) @@ -344,7 +344,7 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen) static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) { - CARD32 data; + uint32_t data; int i = 0; int screen = t->VIP->scrnIndex; @@ -369,12 +369,12 @@ static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) { struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; - CARD8 data8; - CARD32 data, fb_scratch0, fb_scratch1; - CARD32 i; - CARD32 tries = 0; - CARD32 result = 0; - CARD32 seg_id = 0; + uint8_t data8; + uint32_t data, fb_scratch0, fb_scratch1; + uint32_t i; + uint32_t tries = 0; + uint32_t result = 0; + uint32_t seg_id = 0; int screen = t->VIP->scrnIndex; DEBUG("Microcode: before everything: %x\n", data8); @@ -564,9 +564,9 @@ static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) return 0; } -static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0) +static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) { - CARD32 data; + uint32_t data; int i; /* @@ -611,10 +611,10 @@ static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scrat return fb_scratch0; } -static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) +static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); @@ -627,10 +627,10 @@ static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) } #if 0 -static CARD32 dsp_reset(TheatrePtr t) +static uint32_t dsp_reset(TheatrePtr t) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); @@ -643,10 +643,10 @@ static CARD32 dsp_reset(TheatrePtr t) } #endif -static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) +static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); @@ -657,10 +657,10 @@ static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) return result; } -static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) +static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); @@ -672,10 +672,10 @@ static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) return result; } -static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) +static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); @@ -687,10 +687,10 @@ static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) return result; } -static CARD32 dsp_video_standard_detection(TheatrePtr t) +static uint32_t dsp_video_standard_detection(TheatrePtr t) { - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = 0 | (54 & 0xff); @@ -703,11 +703,11 @@ static CARD32 dsp_video_standard_detection(TheatrePtr t) } #if 0 -static CARD32 dsp_get_signallockstatus(TheatrePtr t) +static uint32_t dsp_get_signallockstatus(TheatrePtr t) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = 0 | (77 & 0xff); @@ -720,11 +720,11 @@ static CARD32 dsp_get_signallockstatus(TheatrePtr t) return result; } -static CARD32 dsp_get_signallinenumber(TheatrePtr t) +static uint32_t dsp_get_signallinenumber(TheatrePtr t) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = 0 | (78 & 0xff); @@ -738,11 +738,11 @@ static CARD32 dsp_get_signallinenumber(TheatrePtr t) } #endif -static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) +static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); @@ -754,11 +754,11 @@ static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) return result; } -static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) +static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); @@ -771,11 +771,11 @@ static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) } #if 0 -static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) +static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = 0 | (73 & 0xff); @@ -788,11 +788,11 @@ static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) } #endif -static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) +static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); @@ -804,11 +804,11 @@ static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) return result; } -static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) +static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); @@ -820,11 +820,11 @@ static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) return result; } -static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end) +static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); @@ -837,11 +837,11 @@ static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, return result; } -static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end) +static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); @@ -854,11 +854,11 @@ static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, return result; } -static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) +static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); @@ -870,11 +870,11 @@ static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) return result; } -static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute) +static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); @@ -887,11 +887,11 @@ static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 } #if 0 -static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) +static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); @@ -904,11 +904,11 @@ static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) } #endif -static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode) +static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); @@ -920,11 +920,11 @@ static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, return result; } -static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state) +static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) { - CARD32 fb_scratch1 = 0; - CARD32 fb_scratch0 = 0; - CARD32 result; + uint32_t fb_scratch1 = 0; + uint32_t fb_scratch0 = 0; + uint32_t result; int screen = t->VIP->scrnIndex; fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); @@ -1014,7 +1014,7 @@ fld_V_INT_LENGTH, fld_CRDR_ACTIVE_GAIN, fld_CBDB_ACTIVE_GAIN, fld_DVS_DIRECTION, -fld_DVS_VBI_CARD8_SWAP, +fld_DVS_VBI_UINT8_SWAP, fld_DVS_CLK_SELECT, fld_CONTINUOUS_STREAM, fld_DVSOUT_CLK_DRV, @@ -1096,16 +1096,16 @@ regRT_MAX_REGS typedef struct { - CARD8 size; - CARD32 fld_id; - CARD32 dwRegAddrLSBs; - CARD32 dwFldOffsetLSBs; - CARD32 dwMaskLSBs; - CARD32 addr2; - CARD32 offs2; - CARD32 mask2; - CARD32 dwCurrValue; - CARD32 rw; + uint8_t size; + uint32_t fld_id; + uint32_t dwRegAddrLSBs; + uint32_t dwFldOffsetLSBs; + uint32_t dwMaskLSBs; + uint32_t addr2; + uint32_t offs2; + uint32_t mask2; + uint32_t dwCurrValue; + uint32_t rw; } RTREGMAP; #define READONLY 1 @@ -1193,7 +1193,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, -{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, +{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, @@ -1272,7 +1272,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ }; /* Rage Theatre's register fields default values: */ -CARD32 RT_RegDef[regRT_MAX_REGS]= +uint32_t RT_RegDef[regRT_MAX_REGS]= { fld_tmpReg1_def, fld_tmpReg2_def, @@ -1350,7 +1350,7 @@ fld_V_INT_LENGTH_def, fld_CRDR_ACTIVE_GAIN_def, fld_CBDB_ACTIVE_GAIN_def, fld_DVS_DIRECTION_def, -fld_DVS_VBI_CARD8_SWAP_def, +fld_DVS_VBI_UINT8_SWAP_def, fld_DVS_CLK_SELECT_def, fld_CONTINUOUS_STREAM_def, fld_DVSOUT_CLK_DRV_def, @@ -1429,16 +1429,16 @@ fld_GPIO_6_OUT_def, }; /**************************************************************************** - * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * + * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * * Function: Writes a register field within Rage Theatre * - * Inputs: CARD32 dwReg = register field to be written * - * CARD32 dwData = data that will be written to the reg field * + * Inputs: uint32_t dwReg = register field to be written * + * uint32_t dwData = data that will be written to the reg field * * Outputs: NONE * ****************************************************************************/ -static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) +static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) { - CARD32 dwResult=0; - CARD32 dwValue=0; + uint32_t dwResult=0; + uint32_t dwValue=0; if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) { @@ -1458,14 +1458,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) #if 0 /**************************************************************************** - * ReadRT_fld (CARD32 dwReg) * + * ReadRT_fld (uint32_t dwReg) * * Function: Reads a register field within Rage Theatre * - * Inputs: CARD32 dwReg = register field to be read * - * Outputs: CARD32 - value read from register field * + * Inputs: uint32_t dwReg = register field to be read * + * Outputs: uint32_t - value read from register field * ****************************************************************************/ -static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) +static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) { - CARD32 dwResult=0; + uint32_t dwResult=0; if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) { @@ -1506,7 +1506,7 @@ _X_EXPORT void RT_SetTint (TheatrePtr t, int hue) t->iHue=hue; - dsp_set_tint(t, (CARD8)((hue*255)/2000 + 128)); + dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); } /* RT_SetTint ()... */ @@ -1532,7 +1532,7 @@ _X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) t->iSaturation = Saturation; /* RT200 has saturation in range 0 to 255 with nominal value 128 */ - dsp_set_saturation(t, (CARD8)((Saturation*255)/2000 + 128)); + dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); return; } /* RT_SetSaturation ()...*/ @@ -1560,19 +1560,19 @@ _X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ - dsp_set_brightness(t, (CARD8)((Brightness*255)/2000 + 128)); + dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); return; } /* RT_SetBrightness ()... */ /**************************************************************************** - * RT_SetSharpness (CARD16 wSharpness) * + * RT_SetSharpness (uint16_t wSharpness) * * Function: sets the sharpness level for the Rage Theatre video in * - * Inputs: CARD16 wSharpness - the sharpness value to be set. * + * Inputs: uint16_t wSharpness - the sharpness value to be set. * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) +_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) { switch (wSharpness) { @@ -1615,28 +1615,28 @@ _X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) t->dbContrast = (double) (Contrast+1000.0) / 1000.0; /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ - dsp_set_contrast(t, (CARD8)((Contrast*255)/2000 + 128)); + dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); return; } /* RT_SetContrast ()... */ /**************************************************************************** - * RT_SetInterlace (CARD8 bInterlace) * + * RT_SetInterlace (uint8_t bInterlace) * * Function: to set the interlacing pattern for the Rage Theatre video in * - * Inputs: CARD8 bInterlace * + * Inputs: uint8_t bInterlace * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) +_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) { switch(bInterlace) { case (TRUE): /*DEC_INTERLACE */ WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - t->wInterlaced = (CARD16) RT_DECINTERLACED; + t->wInterlaced = (uint16_t) RT_DECINTERLACED; break; case (FALSE): /*DEC_NONINTERLACE */ WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); - t->wInterlaced = (CARD16) RT_DECNONINTERLACED; + t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; break; default: break; @@ -1648,12 +1648,12 @@ _X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) /**************************************************************************** - * RT_SetStandard (CARD16 wStandard) * + * RT_SetStandard (uint16_t wStandard) * * Function: to set the input standard for the Rage Theatre video in * - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) +_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) { xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", wStandard); @@ -1763,16 +1763,16 @@ _X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) /**************************************************************************** - * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * - * CARD8 fCC_On, CARD8 fVBICap_On) * + * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * + * uint8_t fCC_On, uint8_t fVBICap_On) * * Function: sets the output video size for the Rage Theatre video in * - * Inputs: CARD16 wHorzSize - width of output in pixels * - * CARD16 wVertSize - height of output in pixels (lines) * - * CARD8 fCC_On - enable CC output * - * CARD8 fVBI_Cap_On - enable VBI capture * + * Inputs: uint16_t wHorzSize - width of output in pixels * + * uint16_t wVertSize - height of output in pixels (lines) * + * uint8_t fCC_On - enable CC output * + * uint8_t fVBI_Cap_On - enable VBI capture * * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) +_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) { /* VBI is ignored now */ @@ -1786,15 +1786,15 @@ _X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVe /**************************************************************************** - * RT_SetConnector (CARD16 wStandard, int tunerFlag) * + * RT_SetConnector (uint16_t wStandard, int tunerFlag) * * Function: - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * int tunerFlag * Outputs: NONE * ****************************************************************************/ -_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) +_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) { - CARD32 data; + uint32_t data; t->wConnector = wConnector; @@ -1873,8 +1873,8 @@ _X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) _X_EXPORT void InitTheatre(TheatrePtr t) { - CARD32 data; - CARD32 M, N, P; + uint32_t data; + uint32_t M, N, P; /* this will give 108Mhz at 27Mhz reference */ M = 28; @@ -2006,7 +2006,7 @@ _X_EXPORT void ShutdownTheatre(TheatrePtr t) _X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) { int i; - CARD32 data; + uint32_t data; for(i=0;i<0x900;i+=4) { @@ -2020,7 +2020,7 @@ _X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) void DumpRageTheatreRegsByName(TheatrePtr t) { int i; - CARD32 data; + uint32_t data; struct { char *name; long addr; } rt_reg_list[]={ { "ADC_CNTL ", 0x0400 }, { "ADC_DEBUG ", 0x0404 }, diff --git a/src/theatre_detect.c b/src/theatre_detect.c index 79dcfe4f..7e7f813e 100644 --- a/src/theatre_detect.c +++ b/src/theatre_detect.c @@ -45,18 +45,18 @@ #include "theatre_reg.h" #include "theatre_detect.h" -static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) +static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) { if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); + return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); } /* Unused code - reference */ #if 0 -static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) +static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) { if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); + return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); } #define RT_regw(reg,data) theatre_write(t,(reg),(data)) #endif @@ -69,7 +69,7 @@ _X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) { TheatrePtr t; int i; - CARD32 val; + uint32_t val; char s[20]; b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); @@ -84,10 +84,10 @@ _X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) t->theatre_num = -1; t->mode=MODE_UNINITIALIZED; - b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); + b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); for(i=0;i<4;i++) { - if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) + if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) { if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n", i, diff --git a/src/theatre_reg.h b/src/theatre_reg.h index c6810016..30fafe77 100644 --- a/src/theatre_reg.h +++ b/src/theatre_reg.h @@ -661,215 +661,215 @@ #define DEC_SHARP 1 /* RT Register Field Defaults: */ -#define fld_tmpReg1_def (CARD32) 0x00000000 -#define fld_tmpReg2_def (CARD32) 0x00000001 -#define fld_tmpReg3_def (CARD32) 0x00000002 +#define fld_tmpReg1_def (uint32_t) 0x00000000 +#define fld_tmpReg2_def (uint32_t) 0x00000001 +#define fld_tmpReg3_def (uint32_t) 0x00000002 -#define fld_LP_CONTRAST_def (CARD32) 0x0000006e -#define fld_LP_BRIGHTNESS_def (CARD32) 0x00003ff0 -#define fld_CP_HUE_CNTL_def (CARD32) 0x00000000 -#define fld_LUMA_FILTER_def (CARD32) 0x00000001 -#define fld_H_SCALE_RATIO_def (CARD32) 0x00010000 -#define fld_H_SHARPNESS_def (CARD32) 0x00000000 +#define fld_LP_CONTRAST_def (uint32_t) 0x0000006e +#define fld_LP_BRIGHTNESS_def (uint32_t) 0x00003ff0 +#define fld_CP_HUE_CNTL_def (uint32_t) 0x00000000 +#define fld_LUMA_FILTER_def (uint32_t) 0x00000001 +#define fld_H_SCALE_RATIO_def (uint32_t) 0x00010000 +#define fld_H_SHARPNESS_def (uint32_t) 0x00000000 -#define fld_V_SCALE_RATIO_def (CARD32) 0x00000800 -#define fld_V_DEINTERLACE_ON_def (CARD32) 0x00000001 -#define fld_V_BYPSS_def (CARD32) 0x00000000 -#define fld_V_DITHER_ON_def (CARD32) 0x00000001 -#define fld_EVENF_OFFSET_def (CARD32) 0x00000000 -#define fld_ODDF_OFFSET_def (CARD32) 0x00000000 +#define fld_V_SCALE_RATIO_def (uint32_t) 0x00000800 +#define fld_V_DEINTERLACE_ON_def (uint32_t) 0x00000001 +#define fld_V_BYPSS_def (uint32_t) 0x00000000 +#define fld_V_DITHER_ON_def (uint32_t) 0x00000001 +#define fld_EVENF_OFFSET_def (uint32_t) 0x00000000 +#define fld_ODDF_OFFSET_def (uint32_t) 0x00000000 -#define fld_INTERLACE_DETECTED_def (CARD32) 0x00000000 +#define fld_INTERLACE_DETECTED_def (uint32_t) 0x00000000 -#define fld_VS_LINE_COUNT_def (CARD32) 0x00000000 -#define fld_VS_DETECTED_LINES_def (CARD32) 0x00000000 -#define fld_VS_ITU656_VB_def (CARD32) 0x00000000 +#define fld_VS_LINE_COUNT_def (uint32_t) 0x00000000 +#define fld_VS_DETECTED_LINES_def (uint32_t) 0x00000000 +#define fld_VS_ITU656_VB_def (uint32_t) 0x00000000 -#define fld_VBI_CC_DATA_def (CARD32) 0x00000000 -#define fld_VBI_CC_WT_def (CARD32) 0x00000000 -#define fld_VBI_CC_WT_ACK_def (CARD32) 0x00000000 -#define fld_VBI_CC_HOLD_def (CARD32) 0x00000000 -#define fld_VBI_DECODE_EN_def (CARD32) 0x00000000 +#define fld_VBI_CC_DATA_def (uint32_t) 0x00000000 +#define fld_VBI_CC_WT_def (uint32_t) 0x00000000 +#define fld_VBI_CC_WT_ACK_def (uint32_t) 0x00000000 +#define fld_VBI_CC_HOLD_def (uint32_t) 0x00000000 +#define fld_VBI_DECODE_EN_def (uint32_t) 0x00000000 -#define fld_VBI_CC_DTO_P_def (CARD32) 0x00001802 -#define fld_VBI_20BIT_DTO_P_def (CARD32) 0x0000155c +#define fld_VBI_CC_DTO_P_def (uint32_t) 0x00001802 +#define fld_VBI_20BIT_DTO_P_def (uint32_t) 0x0000155c -#define fld_VBI_CC_LEVEL_def (CARD32) 0x0000003f -#define fld_VBI_20BIT_LEVEL_def (CARD32) 0x00000059 -#define fld_VBI_CLK_RUNIN_GAIN_def (CARD32) 0x0000010f +#define fld_VBI_CC_LEVEL_def (uint32_t) 0x0000003f +#define fld_VBI_20BIT_LEVEL_def (uint32_t) 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def (uint32_t) 0x0000010f -#define fld_H_VBI_WIND_START_def (CARD32) 0x00000041 -#define fld_H_VBI_WIND_END_def (CARD32) 0x00000366 +#define fld_H_VBI_WIND_START_def (uint32_t) 0x00000041 +#define fld_H_VBI_WIND_END_def (uint32_t) 0x00000366 -#define fld_V_VBI_WIND_START_def (CARD32) 0x0B /* instead of 0x0D - V.D. */ -#define fld_V_VBI_WIND_END_def (CARD32) 0x24 +#define fld_V_VBI_WIND_START_def (uint32_t) 0x0B /* instead of 0x0D - V.D. */ +#define fld_V_VBI_WIND_END_def (uint32_t) 0x24 -#define fld_VBI_20BIT_DATA0_def (CARD32) 0x00000000 -#define fld_VBI_20BIT_DATA1_def (CARD32) 0x00000000 -#define fld_VBI_20BIT_WT_def (CARD32) 0x00000000 -#define fld_VBI_20BIT_WT_ACK_def (CARD32) 0x00000000 -#define fld_VBI_20BIT_HOLD_def (CARD32) 0x00000000 +#define fld_VBI_20BIT_DATA0_def (uint32_t) 0x00000000 +#define fld_VBI_20BIT_DATA1_def (uint32_t) 0x00000000 +#define fld_VBI_20BIT_WT_def (uint32_t) 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def (uint32_t) 0x00000000 +#define fld_VBI_20BIT_HOLD_def (uint32_t) 0x00000000 -#define fld_VBI_CAPTURE_ENABLE_def (CARD32) 0x00000000 +#define fld_VBI_CAPTURE_ENABLE_def (uint32_t) 0x00000000 -#define fld_VBI_EDS_DATA_def (CARD32) 0x00000000 -#define fld_VBI_EDS_WT_def (CARD32) 0x00000000 -#define fld_VBI_EDS_WT_ACK_def (CARD32) 0x00000000 -#define fld_VBI_EDS_HOLD_def (CARD32) 0x00000000 +#define fld_VBI_EDS_DATA_def (uint32_t) 0x00000000 +#define fld_VBI_EDS_WT_def (uint32_t) 0x00000000 +#define fld_VBI_EDS_WT_ACK_def (uint32_t) 0x00000000 +#define fld_VBI_EDS_HOLD_def (uint32_t) 0x00000000 -#define fld_VBI_SCALING_RATIO_def (CARD32) 0x00010000 -#define fld_VBI_ALIGNER_ENABLE_def (CARD32) 0x00000000 +#define fld_VBI_SCALING_RATIO_def (uint32_t) 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def (uint32_t) 0x00000000 -#define fld_H_ACTIVE_START_def (CARD32) 0x00000070 -#define fld_H_ACTIVE_END_def (CARD32) 0x000002f0 +#define fld_H_ACTIVE_START_def (uint32_t) 0x00000070 +#define fld_H_ACTIVE_END_def (uint32_t) 0x000002f0 -#define fld_V_ACTIVE_START_def (CARD32) ((22-4)*2+1) -#define fld_V_ACTIVE_END_def (CARD32) ((22+240-4)*2+2) +#define fld_V_ACTIVE_START_def (uint32_t) ((22-4)*2+1) +#define fld_V_ACTIVE_END_def (uint32_t) ((22+240-4)*2+2) -#define fld_CH_HEIGHT_def (CARD32) 0x000000CD -#define fld_CH_KILL_LEVEL_def (CARD32) 0x000000C0 -#define fld_CH_AGC_ERROR_LIM_def (CARD32) 0x00000002 -#define fld_CH_AGC_FILTER_EN_def (CARD32) 0x00000000 -#define fld_CH_AGC_LOOP_SPEED_def (CARD32) 0x00000000 +#define fld_CH_HEIGHT_def (uint32_t) 0x000000CD +#define fld_CH_KILL_LEVEL_def (uint32_t) 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def (uint32_t) 0x00000002 +#define fld_CH_AGC_FILTER_EN_def (uint32_t) 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def (uint32_t) 0x00000000 -#define fld_HUE_ADJ_def (CARD32) 0x00000000 +#define fld_HUE_ADJ_def (uint32_t) 0x00000000 -#define fld_STANDARD_SEL_def (CARD32) 0x00000000 -#define fld_STANDARD_YC_def (CARD32) 0x00000000 +#define fld_STANDARD_SEL_def (uint32_t) 0x00000000 +#define fld_STANDARD_YC_def (uint32_t) 0x00000000 -#define fld_ADC_PDWN_def (CARD32) 0x00000001 -#define fld_INPUT_SELECT_def (CARD32) 0x00000000 +#define fld_ADC_PDWN_def (uint32_t) 0x00000001 +#define fld_INPUT_SELECT_def (uint32_t) 0x00000000 -#define fld_ADC_PREFLO_def (CARD32) 0x00000003 -#define fld_H_SYNC_PULSE_WIDTH_def (CARD32) 0x00000000 -#define fld_HS_GENLOCKED_def (CARD32) 0x00000000 -#define fld_HS_SYNC_IN_WIN_def (CARD32) 0x00000000 +#define fld_ADC_PREFLO_def (uint32_t) 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def (uint32_t) 0x00000000 +#define fld_HS_GENLOCKED_def (uint32_t) 0x00000000 +#define fld_HS_SYNC_IN_WIN_def (uint32_t) 0x00000000 -#define fld_VIN_ASYNC_RST_def (CARD32) 0x00000001 -#define fld_DVS_ASYNC_RST_def (CARD32) 0x00000001 +#define fld_VIN_ASYNC_RST_def (uint32_t) 0x00000001 +#define fld_DVS_ASYNC_RST_def (uint32_t) 0x00000001 /* Vendor IDs: */ -#define fld_VIP_VENDOR_ID_def (CARD32) 0x00001002 -#define fld_VIP_DEVICE_ID_def (CARD32) 0x00004d54 -#define fld_VIP_REVISION_ID_def (CARD32) 0x00000001 +#define fld_VIP_VENDOR_ID_def (uint32_t) 0x00001002 +#define fld_VIP_DEVICE_ID_def (uint32_t) 0x00004d54 +#define fld_VIP_REVISION_ID_def (uint32_t) 0x00000001 /* AGC Delay Register */ -#define fld_BLACK_INT_START_def (CARD32) 0x00000031 -#define fld_BLACK_INT_LENGTH_def (CARD32) 0x0000000f +#define fld_BLACK_INT_START_def (uint32_t) 0x00000031 +#define fld_BLACK_INT_LENGTH_def (uint32_t) 0x0000000f -#define fld_UV_INT_START_def (CARD32) 0x0000003b -#define fld_U_INT_LENGTH_def (CARD32) 0x0000000f -#define fld_V_INT_LENGTH_def (CARD32) 0x0000000f -#define fld_CRDR_ACTIVE_GAIN_def (CARD32) 0x0000007a -#define fld_CBDB_ACTIVE_GAIN_def (CARD32) 0x000000ac +#define fld_UV_INT_START_def (uint32_t) 0x0000003b +#define fld_U_INT_LENGTH_def (uint32_t) 0x0000000f +#define fld_V_INT_LENGTH_def (uint32_t) 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def (uint32_t) 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def (uint32_t) 0x000000ac -#define fld_DVS_DIRECTION_def (CARD32) 0x00000000 -#define fld_DVS_VBI_CARD8_SWAP_def (CARD32) 0x00000000 -#define fld_DVS_CLK_SELECT_def (CARD32) 0x00000000 -#define fld_CONTINUOUS_STREAM_def (CARD32) 0x00000000 -#define fld_DVSOUT_CLK_DRV_def (CARD32) 0x00000001 -#define fld_DVSOUT_DATA_DRV_def (CARD32) 0x00000001 +#define fld_DVS_DIRECTION_def (uint32_t) 0x00000000 +#define fld_DVS_VBI_UINT8_SWAP_def (uint32_t) 0x00000000 +#define fld_DVS_CLK_SELECT_def (uint32_t) 0x00000000 +#define fld_CONTINUOUS_STREAM_def (uint32_t) 0x00000000 +#define fld_DVSOUT_CLK_DRV_def (uint32_t) 0x00000001 +#define fld_DVSOUT_DATA_DRV_def (uint32_t) 0x00000001 -#define fld_COMB_CNTL0_def (CARD32) 0x09438090 -#define fld_COMB_CNTL1_def (CARD32) 0x00000010 +#define fld_COMB_CNTL0_def (uint32_t) 0x09438090 +#define fld_COMB_CNTL1_def (uint32_t) 0x00000010 -#define fld_COMB_CNTL2_def (CARD32) 0x16161010 -#define fld_COMB_LENGTH_def (CARD32) 0x0718038A +#define fld_COMB_CNTL2_def (uint32_t) 0x16161010 +#define fld_COMB_LENGTH_def (uint32_t) 0x0718038A -#define fld_SYNCTIP_REF0_def (CARD32) 0x00000037 -#define fld_SYNCTIP_REF1_def (CARD32) 0x00000029 -#define fld_CLAMP_REF_def (CARD32) 0x0000003B -#define fld_AGC_PEAKWHITE_def (CARD32) 0x000000FF -#define fld_VBI_PEAKWHITE_def (CARD32) 0x000000D2 +#define fld_SYNCTIP_REF0_def (uint32_t) 0x00000037 +#define fld_SYNCTIP_REF1_def (uint32_t) 0x00000029 +#define fld_CLAMP_REF_def (uint32_t) 0x0000003B +#define fld_AGC_PEAKWHITE_def (uint32_t) 0x000000FF +#define fld_VBI_PEAKWHITE_def (uint32_t) 0x000000D2 -#define fld_WPA_THRESHOLD_def (CARD32) 0x000003B0 +#define fld_WPA_THRESHOLD_def (uint32_t) 0x000003B0 -#define fld_WPA_TRIGGER_LO_def (CARD32) 0x000000B4 -#define fld_WPA_TRIGGER_HIGH_def (CARD32) 0x0000021C +#define fld_WPA_TRIGGER_LO_def (uint32_t) 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def (uint32_t) 0x0000021C -#define fld_LOCKOUT_START_def (CARD32) 0x00000206 -#define fld_LOCKOUT_END_def (CARD32) 0x00000021 +#define fld_LOCKOUT_START_def (uint32_t) 0x00000206 +#define fld_LOCKOUT_END_def (uint32_t) 0x00000021 -#define fld_CH_DTO_INC_def (CARD32) 0x00400000 -#define fld_PLL_SGAIN_def (CARD32) 0x00000001 -#define fld_PLL_FGAIN_def (CARD32) 0x00000002 +#define fld_CH_DTO_INC_def (uint32_t) 0x00400000 +#define fld_PLL_SGAIN_def (uint32_t) 0x00000001 +#define fld_PLL_FGAIN_def (uint32_t) 0x00000002 -#define fld_CR_BURST_GAIN_def (CARD32) 0x0000007a -#define fld_CB_BURST_GAIN_def (CARD32) 0x000000ac +#define fld_CR_BURST_GAIN_def (uint32_t) 0x0000007a +#define fld_CB_BURST_GAIN_def (uint32_t) 0x000000ac -#define fld_VERT_LOCKOUT_START_def (CARD32) 0x00000207 -#define fld_VERT_LOCKOUT_END_def (CARD32) 0x0000000E +#define fld_VERT_LOCKOUT_START_def (uint32_t) 0x00000207 +#define fld_VERT_LOCKOUT_END_def (uint32_t) 0x0000000E -#define fld_H_IN_WIND_START_def (CARD32) 0x00000070 -#define fld_V_IN_WIND_START_def (CARD32) 0x00000027 +#define fld_H_IN_WIND_START_def (uint32_t) 0x00000070 +#define fld_V_IN_WIND_START_def (uint32_t) 0x00000027 -#define fld_H_OUT_WIND_WIDTH_def (CARD32) 0x000002f4 +#define fld_H_OUT_WIND_WIDTH_def (uint32_t) 0x000002f4 -#define fld_V_OUT_WIND_WIDTH_def (CARD32) 0x000000f0 +#define fld_V_OUT_WIND_WIDTH_def (uint32_t) 0x000000f0 -#define fld_HS_LINE_TOTAL_def (CARD32) 0x0000038E +#define fld_HS_LINE_TOTAL_def (uint32_t) 0x0000038E -#define fld_MIN_PULSE_WIDTH_def (CARD32) 0x0000002F -#define fld_MAX_PULSE_WIDTH_def (CARD32) 0x00000046 +#define fld_MIN_PULSE_WIDTH_def (uint32_t) 0x0000002F +#define fld_MAX_PULSE_WIDTH_def (uint32_t) 0x00000046 -#define fld_WIN_CLOSE_LIMIT_def (CARD32) 0x0000004D -#define fld_WIN_OPEN_LIMIT_def (CARD32) 0x000001B7 +#define fld_WIN_CLOSE_LIMIT_def (uint32_t) 0x0000004D +#define fld_WIN_OPEN_LIMIT_def (uint32_t) 0x000001B7 -#define fld_VSYNC_INT_TRIGGER_def (CARD32) 0x000002AA +#define fld_VSYNC_INT_TRIGGER_def (uint32_t) 0x000002AA -#define fld_VSYNC_INT_HOLD_def (CARD32) 0x0000001D +#define fld_VSYNC_INT_HOLD_def (uint32_t) 0x0000001D -#define fld_VIN_M0_def (CARD32) 0x00000039 -#define fld_VIN_N0_def (CARD32) 0x0000014c -#define fld_MNFLIP_EN_def (CARD32) 0x00000000 -#define fld_VIN_P_def (CARD32) 0x00000006 -#define fld_REG_CLK_SEL_def (CARD32) 0x00000000 +#define fld_VIN_M0_def (uint32_t) 0x00000039 +#define fld_VIN_N0_def (uint32_t) 0x0000014c +#define fld_MNFLIP_EN_def (uint32_t) 0x00000000 +#define fld_VIN_P_def (uint32_t) 0x00000006 +#define fld_REG_CLK_SEL_def (uint32_t) 0x00000000 -#define fld_VIN_M1_def (CARD32) 0x00000000 -#define fld_VIN_N1_def (CARD32) 0x00000000 -#define fld_VIN_DRIVER_SEL_def (CARD32) 0x00000000 -#define fld_VIN_MNFLIP_REQ_def (CARD32) 0x00000000 -#define fld_VIN_MNFLIP_DONE_def (CARD32) 0x00000000 -#define fld_TV_LOCK_TO_VIN_def (CARD32) 0x00000000 -#define fld_TV_P_FOR_WINCLK_def (CARD32) 0x00000004 +#define fld_VIN_M1_def (uint32_t) 0x00000000 +#define fld_VIN_N1_def (uint32_t) 0x00000000 +#define fld_VIN_DRIVER_SEL_def (uint32_t) 0x00000000 +#define fld_VIN_MNFLIP_REQ_def (uint32_t) 0x00000000 +#define fld_VIN_MNFLIP_DONE_def (uint32_t) 0x00000000 +#define fld_TV_LOCK_TO_VIN_def (uint32_t) 0x00000000 +#define fld_TV_P_FOR_WINCLK_def (uint32_t) 0x00000004 -#define fld_VINRST_def (CARD32) 0x00000001 -#define fld_VIN_CLK_SEL_def (CARD32) 0x00000000 +#define fld_VINRST_def (uint32_t) 0x00000001 +#define fld_VIN_CLK_SEL_def (uint32_t) 0x00000000 -#define fld_VS_FIELD_BLANK_START_def (CARD32) 0x00000206 +#define fld_VS_FIELD_BLANK_START_def (uint32_t) 0x00000206 -#define fld_VS_FIELD_BLANK_END_def (CARD32) 0x0000000A +#define fld_VS_FIELD_BLANK_END_def (uint32_t) 0x0000000A -/*#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000105 */ -#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000001 -#define fld_VS_FRAME_TOTAL_def (CARD32) 0x00000217 +/*#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000001 +#define fld_VS_FRAME_TOTAL_def (uint32_t) 0x00000217 -#define fld_SYNC_TIP_START_def (CARD32) 0x00000372 -#define fld_SYNC_TIP_LENGTH_def (CARD32) 0x0000000F +#define fld_SYNC_TIP_START_def (uint32_t) 0x00000372 +#define fld_SYNC_TIP_LENGTH_def (uint32_t) 0x0000000F -#define fld_GAIN_FORCE_DATA_def (CARD32) 0x00000000 -#define fld_GAIN_FORCE_EN_def (CARD32) 0x00000000 -#define fld_I_CLAMP_SEL_def (CARD32) 0x00000003 -#define fld_I_AGC_SEL_def (CARD32) 0x00000001 -#define fld_EXT_CLAMP_CAP_def (CARD32) 0x00000001 -#define fld_EXT_AGC_CAP_def (CARD32) 0x00000001 -#define fld_DECI_DITHER_EN_def (CARD32) 0x00000001 -#define fld_ADC_PREFHI_def (CARD32) 0x00000000 -#define fld_ADC_CH_GAIN_SEL_def (CARD32) 0x00000001 +#define fld_GAIN_FORCE_DATA_def (uint32_t) 0x00000000 +#define fld_GAIN_FORCE_EN_def (uint32_t) 0x00000000 +#define fld_I_CLAMP_SEL_def (uint32_t) 0x00000003 +#define fld_I_AGC_SEL_def (uint32_t) 0x00000001 +#define fld_EXT_CLAMP_CAP_def (uint32_t) 0x00000001 +#define fld_EXT_AGC_CAP_def (uint32_t) 0x00000001 +#define fld_DECI_DITHER_EN_def (uint32_t) 0x00000001 +#define fld_ADC_PREFHI_def (uint32_t) 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def (uint32_t) 0x00000001 -#define fld_HS_PLL_SGAIN_def (CARD32) 0x00000003 +#define fld_HS_PLL_SGAIN_def (uint32_t) 0x00000003 -#define fld_NREn_def (CARD32) 0x00000000 -#define fld_NRGainCntl_def (CARD32) 0x00000000 -#define fld_NRBWTresh_def (CARD32) 0x00000000 -#define fld_NRGCTresh_def (CARD32) 0x00000000 -#define fld_NRCoefDespeclMode_def (CARD32) 0x00000000 +#define fld_NREn_def (uint32_t) 0x00000000 +#define fld_NRGainCntl_def (uint32_t) 0x00000000 +#define fld_NRBWTresh_def (uint32_t) 0x00000000 +#define fld_NRGCTresh_def (uint32_t) 0x00000000 +#define fld_NRCoefDespeclMode_def (uint32_t) 0x00000000 -#define fld_GPIO_5_OE_def (CARD32) 0x00000000 -#define fld_GPIO_6_OE_def (CARD32) 0x00000000 +#define fld_GPIO_5_OE_def (uint32_t) 0x00000000 +#define fld_GPIO_6_OE_def (uint32_t) 0x00000000 -#define fld_GPIO_5_OUT_def (CARD32) 0x00000000 -#define fld_GPIO_6_OUT_def (CARD32) 0x00000000 +#define fld_GPIO_5_OUT_def (uint32_t) 0x00000000 +#define fld_GPIO_6_OUT_def (uint32_t) 0x00000000 /* End of field default values. */ |