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authorAlex Deucher <agd5f@yahoo.com>2005-06-30 00:33:36 +0000
committerAlex Deucher <agd5f@yahoo.com>2005-06-30 00:33:36 +0000
commita7523e6c0be7a600963e9de10cf0060d16117bf6 (patch)
tree32bc8ff72d0cfcdbc9e2557bda3c7c7560a06083 /src
parentc7e1d31c6aec3a99061c77c4d6f57e2e874e37f1 (diff)
- fix some OUTREGs that should be OUTPLLs in dynamicclocks code
Diffstat (limited to 'src')
-rw-r--r--src/radeon_driver.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 22ae1657..6c9d9d53 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -8856,7 +8856,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode)
RADEON_SCLK_FORCE_IDCT |
RADEON_SCLK_FORCE_VIP);
}
- OUTREG(RADEON_SCLK_CNTL, tmp);
+ OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
usleep(16000);
@@ -8874,7 +8874,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode)
tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
tmp &= ~(RADEON_FORCEON_MCLKA |
RADEON_FORCEON_YCLKA);
- OUTREG(RADEON_MCLK_CNTL, tmp);
+ OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
usleep(16000);
}
@@ -8896,7 +8896,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode)
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
RADEON_PIXCLK_TMDS_ALWAYS_ONb);
- OUTREG(RADEON_PIXCLKS_CNTL, tmp);
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
usleep(16000);
tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
@@ -9077,7 +9077,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode)
RADEON_CFG_ATI_REV_A13)) {
tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL);
tmp |= RADEON_TCL_BYPASS_DISABLE;
- OUTREG(RADEON_PLL_PWRMGT_CNTL, tmp);
+ OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp);
}
usleep(15000);