diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-02-05 17:31:43 -0500 |
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committer | Alex Deucher <alexdeucher@gmail.com> | 2009-02-05 17:31:43 -0500 |
commit | bf74055f543e7f0664741620fb1fe827ebc12711 (patch) | |
tree | 2514162b7551ef07f01b9beea5937b69fde1ca3f /src | |
parent | b24827c9d211e8a35da53b665385a7733d19910d (diff) |
r6xx/r7xx EXA: fix corruption when doing sw access
need to wait until the engine is idle. Ideally we wait
on a timestamp shadowed in memory, but polling the
GRBM_STATUS reg will do for now.
Diffstat (limited to 'src')
-rw-r--r-- | src/r600_exa.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index 4d378049..cca82cb5 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -2003,6 +2003,23 @@ static void R600DoneComposite(PixmapPtr pDst) R600CPFlushIndirect(pScrn, accel_state->ib); } +/* really would be better to wait on a timestamp shadowed in memory, + * but this will do for now. + */ +static Bool +R600WaitforIdlePoll(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + uint32_t i; + + for (i = 0; i < 1000000; i++) { + if ((INREG(GRBM_STATUS) & GUI_ACTIVE_bit) == 0) + return TRUE; + } + return FALSE; +} + static Bool R600UploadToScreen(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) @@ -3398,6 +3415,8 @@ R600PrepareAccess(PixmapPtr pPix, int index) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + R600WaitforIdlePoll(pScrn); + //flush HDP read/write caches OUTREG(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |