ontario: add UMS modesetting support

Accel not enabled yet.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>

5 files changed, 49 insertions, 20 deletions

diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6bcc293f..006905be 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -731,9 +731,17 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
 	else
 	    disp_data.v3.ucLaneNum = 4;
 
-	if (radeon_output->linkb) {
-	    disp_data.v3.acConfig.ucLinkSel = 1;
-	    disp_data.v2.acConfig.ucEncoderSel = 1;
+	if (IS_DCE41_VARIANT) {
+	    if (radeon_output->dig_encoder)
+		disp_data.v3.acConfig.ucEncoderSel = 1;
+
+	    if (radeon_output->linkb)
+		disp_data.v3.acConfig.ucLinkSel = 1;
+	} else {
+	    if (radeon_output->linkb) {
+		disp_data.v3.acConfig.ucLinkSel = 1;
+		disp_data.v2.acConfig.ucEncoderSel = 1;
+	    }
 	}
 
 	// select the PLL for the UNIPHY
@@ -1630,6 +1638,12 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
         mode == ATOM_ENCODER_MODE_CV)
         return;
 
+    if (IS_DCE41_VARIANT) {
+        RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+        radeon_output->dig_encoder = radeon_crtc->crtc_id;
+        return;
+    }
+
     if (IS_DCE4_VARIANT) {
         radeon_encoder = radeon_get_encoder(output);
 
diff --git a/src/radeon.h b/src/radeon.h
index 21c6d1c5..84d3563b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -358,6 +358,7 @@ typedef enum {
     CHIP_FAMILY_JUNIPER,
     CHIP_FAMILY_CYPRESS,
     CHIP_FAMILY_HEMLOCK,
+    CHIP_FAMILY_PALM,
     CHIP_FAMILY_LAST
 } RADEONChipFamily;
 
@@ -387,6 +388,8 @@ typedef enum {
 
 #define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR))
 
+#define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM))
+
 #define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR)
 
 #define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600)
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5f4a0a7b..550bd39b 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -885,7 +885,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
     }
 
     /* 6 crtcs on DCE4 chips */
-    if (IS_DCE4_VARIANT && ((mask & 3) == 3)) {
+    if (IS_DCE4_VARIANT && ((mask & 3) == 3) && !IS_DCE41_VARIANT) {
 	for (i = 2; i < RADEON_MAX_CRTC; i++) {
 	    pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
 	    if (!pRADEONEnt->pCrtc[i])
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2e7046fd..3900b096 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1424,7 +1424,12 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
     /* We shouldn't use info->videoRam here which might have been clipped
      * but the real video RAM instead
      */
-    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+    if (info->ChipFamily >= CHIP_FAMILY_PALM) {
+	/* size in bytes on fusion */
+	mem_size = INREG(R600_CONFIG_MEMSIZE);
+	/* size in MB on fusion */
+	aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024;
+    } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
 	/* size in MB on evergreen */
 	/* XXX watch for overflow!!! */
 	mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024;
@@ -1469,7 +1474,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
 	(info->ChipFamily != CHIP_FAMILY_RS690) &&
 	(info->ChipFamily != CHIP_FAMILY_RS740) &&
 	(info->ChipFamily != CHIP_FAMILY_RS780) &&
-	(info->ChipFamily != CHIP_FAMILY_RS880)) {
+	(info->ChipFamily != CHIP_FAMILY_RS880) &&
+	(info->ChipFamily != CHIP_FAMILY_PALM)) {
 	if (info->IsIGP)
 	    info->mc_fb_location = INREG(RADEON_NB_TOM);
 	else
@@ -1650,7 +1656,7 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
     unsigned char  byte;
 
     if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
-	/* size in MB */
+	/* size in MB on evergreen and fusion */
 	aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024;
     else if (info->ChipFamily >= CHIP_FAMILY_R600)
 	aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
@@ -1735,7 +1741,10 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
 
 	OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
     } else {
-	if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
+	if (info->ChipFamily >= CHIP_FAMILY_PALM)
+	    /* R600_CONFIG_MEMSIZE is bytes on fusion */
+	    pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
+	else if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
 	    /* R600_CONFIG_MEMSIZE is MB on evergreen */
 	    /* XXX watch for overflow!!! */
 	    pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024;
@@ -3949,21 +3958,23 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
 	    OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
 	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
-	    OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+	    if (!IS_DCE41_VARIANT) {
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+		OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
-	    OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+		OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
-	    OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+		OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
-	    OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
-	    tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+		OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+		tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+	    }
 
 	    usleep(10000);
 	    timeout = 0;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 0cd419f2..76460602 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -263,6 +263,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
     }
 
     if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
+	(info->ChipFamily >= CHIP_FAMILY_PALM) ||
 	(!RADEONIsAccelWorking(pScrn))) {
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		   "GPU accel disabled or not working, using shadowfb for KMS\n");