diff options
| -rw-r--r-- | src/radeon_reg.h | 6 | ||||
| -rw-r--r-- | src/radeon_textured_video.c | 1 | ||||
| -rw-r--r-- | src/radeon_textured_videofuncs.c | 786 | ||||
| -rw-r--r-- | src/radeon_video.h | 1 |
4 files changed, 762 insertions, 32 deletions
diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 1d352361..8b47dba4 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -4346,6 +4346,7 @@ #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 +#define R300_TX_FILTER0_1 0x4404 # define R300_TX_CLAMP_S(x) (x << 0) # define R300_TX_CLAMP_T(x) (x << 3) # define R300_TX_CLAMP_R(x) (x << 6) @@ -4363,7 +4364,9 @@ # define R300_TX_MIN_FILTER_LINEAR (2 << 11) # define R300_TX_ID_SHIFT 28 #define R300_TX_FILTER1_0 0x4440 +#define R300_TX_FILTER1_1 0x4444 #define R300_TX_FORMAT0_0 0x4480 +#define R300_TX_FORMAT0_1 0x4484 # define R300_TXWIDTH_SHIFT 0 # define R300_TXHEIGHT_SHIFT 11 # define R300_NUM_LEVELS_SHIFT 26 @@ -4371,6 +4374,7 @@ # define R300_TXPROJECTED (1 << 30) # define R300_TXPITCH_EN (1 << 31) #define R300_TX_FORMAT1_0 0x44c0 +#define R300_TX_FORMAT1_1 0x44c4 # define R300_TX_FORMAT_X8 0x0 # define R300_TX_FORMAT_X16 0x1 # define R300_TX_FORMAT_Y4X4 0x2 @@ -4444,10 +4448,12 @@ # define R300_TX_FORMAT_SWAP_YUV (1 << 24) #define R300_TX_FORMAT2_0 0x4500 +#define R300_TX_FORMAT2_1 0x4504 # define R500_TXWIDTH_11 (1 << 15) # define R500_TXHEIGHT_11 (1 << 16) #define R300_TX_OFFSET_0 0x4540 +#define R300_TX_OFFSET_1 0x4544 # define R300_ENDIAN_SWAP_16_BIT (1 << 0) # define R300_ENDIAN_SWAP_32_BIT (2 << 0) # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c index 15f1c5ce..6c0890f7 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -205,6 +205,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->bicubic_offset = RADEONAllocateMemory(pScrn, &pPriv->bicubic_memory, sizeof(bicubic_tex_128)); + pPriv->bicubic_src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset; if (pPriv->bicubic_offset == 0) pPriv->bicubic_enabled = FALSE; } diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index d39f74dd..28074221 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -194,6 +194,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txenable = R300_TEX_0_ENABLE; + if (pPriv->bicubic_enabled) { + /* Size is 128x1 */ + txformat0 = (0x80 << R300_TXWIDTH_SHIFT) | (0x1 << R300_TXHEIGHT_SHIFT); + /* Format is 32-bit floats, 4bpp */ + txformat1 = R300_TX_FORMAT_FL_R32G32B32A32; + + BEGIN_VIDEO(6); + /* No filtering */ + OUT_VIDEO_REG(R300_TX_FILTER0_1, 0); + OUT_VIDEO_REG(R300_TX_FILTER1_1, 0); + OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0); + OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1); + /* No pitch changes */ + OUT_VIDEO_REG(R300_TX_FORMAT2_1, 0); + OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset); + FINISH_VIDEO(); + + /* Enable tex 1 */ + txenable |= R300_TEX_1_ENABLE; + } + /* setup the VAP */ if (info->has_tcl) BEGIN_VIDEO(6); @@ -313,24 +334,730 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R300_ALU_ALPHA_CLAMP)); FINISH_VIDEO(); } else { - BEGIN_VIDEO(18); - /* 2 components: 2 for tex0 */ - OUT_VIDEO_REG(R300_RS_COUNT, - ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | - R300_RS_COUNT_HIRES_EN)); - - /* R300_INST_COUNT_RS - highest RS instruction used */ - OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); - + /* These are the same whether or not bicubic is enabled! */ + BEGIN_VIDEO(4); OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | - R500_US_CODE_END_ADDR(1))); + R500_US_CODE_END_ADDR(1))); OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | - R500_US_CODE_RANGE_SIZE(1))); + R500_US_CODE_RANGE_SIZE(1))); OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); + FINISH_VIDEO(); + + if (pPriv->bicubic_enabled) { + BEGIN_VIDEO(142); + /* This one's set in RADEONInit3DEngine, but we need to set + * it again, in order to enable all four components! */ +// OUT_VIDEO_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | +// (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | +// (4 << R500_RS_IP_TEX_PTR_R_SHIFT) | +// (5 << R500_RS_IP_TEX_PTR_Q_SHIFT))); + /* 6 tex components; 2 from tex0 and all four from tex1 */ +// OUT_VIDEO_REG(R300_RS_COUNT, +// ((6 << R300_RS_COUNT_IT_COUNT_SHIFT) | +// R300_RS_COUNT_HIRES_EN)); +// OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | +// R300_TX_OFFSET_RS(6)); + + /* Pixel stack frame size. */ + OUT_VIDEO_REG(R500_US_PIXSIZE, R500_PIX_SIZE(16)); + + /* Pixel shader. + * I've gone ahead and annotated each instruction, since this + * thing is MASSIVE. :3 */ + /* TEX temp0, input0.xxxx, tex0, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_R | + R500_TEX_SRC_R_SWIZ_R | + R500_TEX_SRC_Q_SWIZ_R | + R500_TEX_DST_ADDR(2) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + + /* TEX temp1, input0.yyyy, tex0, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | + R500_TEX_SRC_S_SWIZ_G | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_SRC_R_SWIZ_G | + R500_TEX_SRC_Q_SWIZ_G | + R500_TEX_DST_ADDR(3) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + + /* MUL temp2, const0, temp0.yyyy */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0)); + + /* MUL temp3, const0, -temp0.xxxx */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_R | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_R | + R500_ALPHA_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0)); + + /* MAD temp4, const1, temp1.yyyy, temp2 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(3) | + R500_RGB_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(3) | + R500_ALPHA_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* MAD temp5, const1, temp1.yyyy, temp3 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(3) | + R500_RGB_ADDR2(5))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(3) | + R500_ALPHA_ADDR2(5))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_G)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* MAD temp2, const1, -temp1.xxxx, temp2 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(3) | + R500_RGB_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(3) | + R500_ALPHA_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_R | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_R)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* MAD temp3, const1, -temp1.xxxx, temp3 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | + R500_RGB_ADDR0_CONST | + R500_RGB_ADDR1(3) | + R500_RGB_ADDR2(5))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | + R500_ALPHA_ADDR0_CONST | + R500_ALPHA_ADDR1(3) | + R500_ALPHA_ADDR2(5))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_R | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_R)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* ADD temp2, temp2, input0 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) | + R500_RGB_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) | + R500_ALPHA_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* ADD temp3, temp3, input0 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) | + R500_RGB_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) | + R500_ALPHA_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* ADD temp4, temp4, input0 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(6) | + R500_RGB_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(6) | + R500_ALPHA_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(6) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(6) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* ADD temp5, temp5, input0 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(7) | + R500_RGB_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(7) | + R500_ALPHA_ADDR2(0))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(7) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(7) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* TEX temp2, temp2, tex1, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(4) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_SRC_R_SWIZ_B | + R500_TEX_SRC_Q_SWIZ_A | + R500_TEX_DST_ADDR(4) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - /* tex inst */ - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + /* TEX temp3, temp3, tex1, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(5) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_SRC_R_SWIZ_B | + R500_TEX_SRC_Q_SWIZ_A | + R500_TEX_DST_ADDR(5) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + + /* TEX temp4, temp4, tex1, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(6) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_SRC_R_SWIZ_B | + R500_TEX_SRC_Q_SWIZ_A | + R500_TEX_DST_ADDR(6) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + + /* TEX temp5, temp5, tex1, 1D */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(7) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_SRC_R_SWIZ_B | + R500_TEX_SRC_Q_SWIZ_A | + R500_TEX_DST_ADDR(7) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + + /* LRP temp3, temp1.zzzz, temp3, temp5 -> + * - ADD temp6, temp3, -temp5 + * - MAD temp3, temp1.zzzz, temp6, temp5 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) | + R500_RGB_ADDR2(7))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) | + R500_ALPHA_ADDR2(7))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A | + R500_ALU_RGBA_ALPHA_MOD_C_NEG)); + /* 2nd inst */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) | + R500_RGB_ADDR1(8) | + R500_RGB_ADDR2(7))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) | + R500_ALPHA_ADDR1(8) | + R500_ALPHA_ADDR2(7))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_B | + R500_ALU_RGB_G_SWIZ_A_B | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(5) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_B | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(5) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* LRP temp2, temp1.zzzz, temp2, temp4 -> + * - ADD temp6, temp2, -temp4 + * - MAD temp2, temp1.zzzz, temp6, temp4 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) | + R500_RGB_ADDR2(6))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) | + R500_ALPHA_ADDR2(6))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A | + R500_ALU_RGBA_ALPHA_MOD_C_NEG)); + /* 2nd inst */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) | + R500_RGB_ADDR1(8) | + R500_RGB_ADDR2(6))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) | + R500_ALPHA_ADDR1(8) | + R500_ALPHA_ADDR2(6))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_B | + R500_ALU_RGB_G_SWIZ_A_B | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_B | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* LRP output, temp0.zzzz, temp3, temp2 -> + * - ADD temp6, temp3, -temp2 + * - MAD temp3, temp0.zzzz, temp6, temp2 */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(5) | + R500_RGB_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(5) | + R500_ALPHA_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | + R500_ALU_RGB_G_SWIZ_A_1 | + R500_ALU_RGB_B_SWIZ_A_1 | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(8) | + R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_1 | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(8) | + R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A | + R500_ALU_RGBA_ALPHA_MOD_C_NEG)); + /* 2nd inst */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | + R500_INST_LAST | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) | + R500_RGB_ADDR1(8) | + R500_RGB_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) | + R500_ALPHA_ADDR1(8) | + R500_ALPHA_ADDR2(4))); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_B | + R500_ALU_RGB_G_SWIZ_A_B | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC1 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_G_SWIZ_B_G | + R500_ALU_RGB_B_SWIZ_B_B | + R500_ALU_RGB_MOD_B_NEG)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_B | + R500_ALPHA_SWIZ_B_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_SEL_C_SRC2 | + R500_ALU_RGBA_R_SWIZ_R | + R500_ALU_RGBA_G_SWIZ_G | + R500_ALU_RGBA_B_SWIZ_B | + R500_ALU_RGBA_A_SWIZ_A)); + + /* Shader constants. */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, (1 << 16)); + + /* const0 = {1 / texture[0].width, 0, 0, 0} */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->w)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + /* const1 = {0, 1 / -texture[0].height, 0, 0) */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (uint32_t)(1/pPriv->h)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x0); + + FINISH_VIDEO(); + } else { + BEGIN_VIDEO(14); + /* 2 components: 2 for tex0 */ + OUT_VIDEO_REG(R300_RS_COUNT, + ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | + R300_RS_COUNT_HIRES_EN)); + + /* R300_INST_COUNT_RS - highest RS instruction used */ + OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); + + /* tex inst */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | @@ -338,13 +1065,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | @@ -352,7 +1077,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | @@ -362,11 +1087,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - /* ALU inst */ - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | + /* ALU inst */ + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | R500_INST_RGB_OMASK_R | @@ -375,19 +1100,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST)); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | @@ -395,17 +1118,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1)); - - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0)); - FINISH_VIDEO(); + FINISH_VIDEO(); + } } BEGIN_VIDEO(5); diff --git a/src/radeon_video.h b/src/radeon_video.h index e81ac945..b9ead1c5 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h @@ -95,6 +95,7 @@ typedef struct { void *bicubic_memory; int bicubic_offset; Bool bicubic_enabled; + uint32_t bicubic_src_offset; Atom device_id, location_id, instance_id; |