diff options
| -rw-r--r-- | src/radeon_exa_render.c | 111 | ||||
| -rw-r--r-- | src/radeon_reg.h | 20 | ||||
| -rw-r--r-- | src/radeon_textured_videofuncs.c | 98 |
3 files changed, 169 insertions, 60 deletions
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 1a4be277..4606cc24 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -1202,53 +1202,96 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, OUT_ACCEL_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); - OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); + OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); OUT_ACCEL_REG(R300_RS_INST_COUNT, 0); OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_ACCEL_REG(R300_US_PIXSIZE, 0); OUT_ACCEL_REG(R500_US_FC_CTRL, 0); - OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); + OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | + R500_US_CODE_END_ADDR(1))); + OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | + R500_US_CODE_RANGE_SIZE(1))); OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); // 7807 - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | - R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK); - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | - R500_TEX_IGNORE_UNCOVERED); - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | - R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | - R500_TEX_DST_A_SWIZ_A); - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // TEX_ADDR_DXDY + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_DST_ADDR(0) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | + R500_DX_S_SWIZ_R | + R500_DX_T_SWIZ_R | + R500_DX_R_SWIZ_R | + R500_DX_Q_SWIZ_R | + R500_DY_ADDR(0) | + R500_DY_S_SWIZ_R | + R500_DY_T_SWIZ_R | + R500_DY_R_SWIZ_R | + R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz // 0x78105 - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | - R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK); - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | R500_RGB_SRCP_OP_1_MINUS_2RGB0); //0x10040000 - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | R500_ALPHA_SRCP_OP_1_MINUS_2A0); //0x10040000 - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, - R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1);//0x00db0220 - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_MAD | - R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1);//0x00c0c000) - - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_MAD | - R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0);//0x20490000 + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK)); + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST | + R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000 + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST | + R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000 + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_1 | + R500_ALU_RGB_B_SWIZ_B_1 | + R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220 + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_1));//0x00c0c000) + + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0));//0x20490000 FINISH_ACCEL(); } diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 9ae60918..7d9bad39 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -4309,10 +4309,10 @@ # define R300_ALU_RGB_SEL_C(x) (x << 14) # define R300_ALU_RGB_MOD_C(x) (x << 19) # define R300_ALU_RGB_SRCP_OP(x) (x << 21) -# define R300_ALU_RGB_SRCP_OP0 0 /* 1.0 - 2.0 * RGB0 */ -# define R300_ALU_RGB_SRCP_OP1 1 /* RGB1 - RGB0 */ -# define R300_ALU_RGB_SRCP_OP2 2 /* RGB1 + RGB0 */ -# define R300_ALU_RGB_SRCP_OP3 3 /* 1.0 - RGB0 */ +# define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0 +# define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1 +# define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2 +# define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3 # define R300_ALU_RGB_OP(x) (x << 23) # define R300_ALU_RGB_OP_MAD 0 # define R300_ALU_RGB_OP_DP3 1 @@ -4383,10 +4383,10 @@ # define R300_ALU_ALPHA_SEL_C(x) (x << 14) # define R300_ALU_ALPHA_MOD_C(x) (x << 19) # define R300_ALU_ALPHA_SRCP_OP(x) (x << 21) -# define R300_ALU_ALPHA_SRCP_OP0 0 /* 1.0 - 2.0 * A0 */ -# define R300_ALU_ALPHA_SRCP_OP1 1 /* A1 - A0 */ -# define R300_ALU_ALPHA_SRCP_OP2 2 /* A1 + A0 */ -# define R300_ALU_ALPHA_SRCP_OP3 3 /* 1.0 - A0 */ +# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0 +# define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1 +# define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2 +# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3 # define R300_ALU_ALPHA_OP(x) (x << 23) # define R300_ALU_ALPHA_OP_MAD 0 # define R300_ALU_ALPHA_OP_DP 1 @@ -4560,7 +4560,7 @@ # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) -# define R500_ALPHA_SRCP_OP_1_PLUS_A0 (3 << 30) +# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) #define R500_US_ALU_RGBA_INST_0 0xb000 # define R500_ALU_RGBA_OP_MAD (0 << 0) # define R500_ALU_RGBA_OP_DP3 (1 << 0) @@ -4713,7 +4713,7 @@ # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) -# define R500_RGB_SRCP_OP_1_PLUS_RGB0 (3 << 30) +# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) #define R500_US_CMN_INST_0 0xb800 # define R500_INST_TYPE_ALU (0 << 0) # define R500_INST_TYPE_OUT (1 << 0) diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index 3a7eb9cc..a0bb8288 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -382,30 +382,96 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv OUT_VIDEO_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); - OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); + OUT_VIDEO_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); OUT_VIDEO_REG(R300_RS_INST_COUNT, 0); OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_VIDEO_REG(R300_US_PIXSIZE, 0); OUT_VIDEO_REG(R500_US_FC_CTRL, 0); - OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); + OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | + R500_US_CODE_END_ADDR(1))); + OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | + R500_US_CODE_RANGE_SIZE(1))); OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00078105); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00db0220); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00c0c000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x20490000); + // 7807 + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | + R500_INST_RGB_WMASK_B | + R500_INST_ALPHA_WMASK)); + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | + R500_TEX_SRC_S_SWIZ_R | + R500_TEX_SRC_T_SWIZ_G | + R500_TEX_DST_ADDR(0) | + R500_TEX_DST_R_SWIZ_R | + R500_TEX_DST_G_SWIZ_G | + R500_TEX_DST_B_SWIZ_B | + R500_TEX_DST_A_SWIZ_A)); + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | + R500_DX_S_SWIZ_R | + R500_DX_T_SWIZ_R | + R500_DX_R_SWIZ_R | + R500_DX_Q_SWIZ_R | + R500_DY_ADDR(0) | + R500_DY_S_SWIZ_R | + R500_DY_T_SWIZ_R | + R500_DY_R_SWIZ_R | + R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + + // 0x78105 + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK)); + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST | + R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000 + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST | + R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000 + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_1 | + R500_ALU_RGB_B_SWIZ_B_1 | + R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220 + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_1));//0x00c0c000) + + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0));//0x20490000 FINISH_VIDEO(); } |