diff options
| -rw-r--r-- | configure.ac | 4 | ||||
| -rw-r--r-- | src/radeon_atombios.c | 2 | ||||
| -rw-r--r-- | src/radeon_atombios.h | 3 | ||||
| -rw-r--r-- | src/radeon_bios.c | 231 | ||||
| -rw-r--r-- | src/radeon_driver.c | 63 | ||||
| -rw-r--r-- | src/radeon_reg.h | 23 |
6 files changed, 282 insertions, 44 deletions
diff --git a/configure.ac b/configure.ac index ab8bd97c..a63f5e86 100644 --- a/configure.ac +++ b/configure.ac @@ -183,6 +183,10 @@ AC_CHECK_DECL(xf86RotateFreeShadow, #include <windowstr.h> #include <xf86Crtc.h>]) +AC_CHECK_DECL(pci_device_enable, + [AC_DEFINE(HAVE_PCI_DEVICE_ENABLE, 1, [Have pci_device_enable prototype])], + [], + [#include <pciaccess.h>]) AC_CHECK_DECL(XSERVER_LIBPCIACCESS, [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index db273629..5cc21d52 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -492,7 +492,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, } # ifdef ATOM_BIOS_PARSER -static Bool +Bool rhdAtomASICInit(atomBiosHandlePtr handle) { ASIC_INIT_PS_ALLOCATION asicInit; diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h index b4a19aad..fe7044d0 100644 --- a/src/radeon_atombios.h +++ b/src/radeon_atombios.h @@ -131,6 +131,9 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); extern void atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor); +Bool +rhdAtomASICInit(atomBiosHandlePtr handle); + # include "xf86int10.h" # ifdef ATOM_BIOS_PARSER # define INT8 INT8 diff --git a/src/radeon_bios.c b/src/radeon_bios.c index be72339a..bc041c3f 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -65,9 +65,208 @@ typedef enum CONNECTOR_UNSUPPORTED_LEGACY } RADEONLegacyConnectorType; +static Bool +radeon_read_bios(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + +#ifdef XSERVER_LIBPCIACCESS + if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Failed to read PCI ROM!\n"); + return FALSE; + } +#else + xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected in PCI space!\n"); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Attempting to read Video BIOS from " + "legacy ISA space!\n"); + info->BIOSAddr = 0x000c0000; + xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, + RADEON_VBIOS_SIZE, info->VBIOS); + } +#endif + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) + return FALSE; + else + return TRUE; +} + +static Bool +radeon_read_unposted_bios(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + Bool ret; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); + + if (info->ChipFamily >= CHIP_FAMILY_R600) { + uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); + uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); + uint32_t rom_cntl = INREG(R600_ROM_CNTL); + uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); + uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); + uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); + uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); + uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); + uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); + + /* disable VIP */ + OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + /* enable the rom */ + OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + /* Disable VGA mode */ + OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + + OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | + (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | + R600_SCK_OVERWRITE)); + + OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); + + OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); + + OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); + + OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); + + OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); + + OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); + + ret = radeon_read_bios(pScrn); + + /* restore regs */ + OUTREG(RADEON_VIPH_CONTROL, viph_control); + OUTREG(RADEON_BUS_CNTL, bus_cntl); + OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); + OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); + OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + OUTREG(R600_ROM_CNTL, rom_cntl); + OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); + OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); + OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); + OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); + OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); + OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); + + } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { + uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); + uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); + uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); + uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); + uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); + uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); + + OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | + (0xc << RADEON_SCK_PRESCALE_SHIFT))); + + OUTREG(RADEON_GPIOPAD_A, 0); + OUTREG(RADEON_GPIOPAD_EN, 0); + OUTREG(RADEON_GPIOPAD_MASK, 0); + + /* disable VIP */ + OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + /* enable the rom */ + OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + /* Disable VGA mode */ + OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | + AVIVO_DVGA_CONTROL_TIMING_SELECT))); + OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + + ret = radeon_read_bios(pScrn); + + /* restore regs */ + OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); + OUTREG(RADEON_VIPH_CONTROL, viph_control); + OUTREG(RADEON_BUS_CNTL, bus_cntl); + OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); + OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); + OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + OUTREG(RADEON_GPIOPAD_A, gpiopad_a); + OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); + OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); + + } else { + uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); + uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); + uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); + uint32_t crtc2_gen_cntl = 0; + uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); + uint32_t fp2_gen_cntl = 0; + + if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) + fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); + + if (pRADEONEnt->HasCRTC2) + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); + + OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | + (0xc << RADEON_SCK_PRESCALE_SHIFT))); + + /* disable VIP */ + OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + /* enable the rom */ + OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + /* Turn off mem requests and CRTC for both controllers */ + OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | + (RADEON_CRTC_DISP_REQ_EN_B | + RADEON_CRTC_EXT_DISP_EN))); + if (pRADEONEnt->HasCRTC2) + OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | + RADEON_CRTC2_DISP_REQ_EN_B)); + + /* Turn off CRTC */ + OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | + (RADEON_CRTC_SYNC_TRISTAT | + RADEON_CRTC_DISPLAY_DIS))); + + if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) + OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); + + ret = radeon_read_bios(pScrn); + + /* restore regs */ + OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); + OUTREG(RADEON_VIPH_CONTROL, viph_control); + OUTREG(RADEON_BUS_CNTL, bus_cntl); + OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); + if (pRADEONEnt->HasCRTC2) + OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); + if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + } + return ret; +} /* Read the Video BIOS block and the FP registers (if applicable). */ -Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +Bool +RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { RADEONInfoPtr info = RADEONPTR(pScrn); int tmp; @@ -88,25 +287,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->BIOSAddr = pInt10->BIOSseg << 4; (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), RADEON_VBIOS_SIZE); - } else { -#ifdef XSERVER_LIBPCIACCESS - if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Failed to read PCI ROM!\n"); - } -#else - xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected in PCI space!\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Attempting to read Video BIOS from " - "legacy ISA space!\n"); - info->BIOSAddr = 0x000c0000; - xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, - RADEON_VBIOS_SIZE, info->VBIOS); - } -#endif + } else if (!radeon_read_bios(pScrn)) { + (void)radeon_read_unposted_bios(pScrn); } } @@ -160,7 +342,6 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->IsAtomBios ? "ATOM":"Legacy"); if (info->IsAtomBios) { -#if 1 AtomBiosArgRec atomBiosArg; if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) @@ -194,8 +375,14 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_REF_CLOCK, &atomBiosArg); -#endif info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); + } else { + /* non-primary card may need posting */ + if (!pInt10) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n"); + RADEONGetBIOSInitTableOffsets(pScrn); + RADEONPostCardFromBIOSTables(pScrn); + } } return TRUE; diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 733e9c6b..91421b5f 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1631,7 +1631,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) break; } } - + switch (info->Chipset) { case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ case PCI_CHIP_RN50_5969: @@ -1980,6 +1980,20 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) unsigned char *RADEONMMIO = info->MMIO; uint32_t fp2_gen_ctl_save = 0; +#ifdef XSERVER_LIBPCIACCESS +#if HAVE_PCI_DEVICE_ENABLE + pci_device_enable(info->PciInfo); +#endif +#endif + /* don't need int10 on atom cards. + * in theory all radeons, but the older stuff + * isn't 100% yet + */ + if ((info->ChipFamily == CHIP_FAMILY_R420) || + (info->ChipFamily == CHIP_FAMILY_RV410) || + (info->ChipFamily >= CHIP_FAMILY_RV515)) + return TRUE; + if (xf86LoadSubModule(pScrn, "int10")) { /* The VGA BIOS on the RV100/QY cannot be read when the digital output * is enabled. Clear and restore FP2_ON around int10 to avoid this. @@ -1991,13 +2005,15 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); } } - + xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); *ppInt10 = xf86InitInt10(info->pEnt->index); - if (fp2_gen_ctl_save & RADEON_FP2_ON) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); + if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { + if (fp2_gen_ctl_save & RADEON_FP2_ON) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); + } } } #endif @@ -2470,10 +2486,6 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { RADEONGetBIOSInfo(pScrn, pInt10); -#if 0 - RADEONGetBIOSInitTableOffsets(pScrn); - RADEONPostCardFromBIOSTables(pScrn); -#endif } static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) @@ -2747,14 +2759,14 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info->DispPriority = 1; } + if (!RADEONPreInitChipType(pScrn)) + goto fail; + if (!RADEONPreInitInt10(pScrn, &pInt10)) goto fail; RADEONPostInt10Check(pScrn, int10_save); - if (!RADEONPreInitChipType(pScrn)) - goto fail; - RADEONPreInitBIOS(pScrn, pInt10); #ifdef XF86DRI @@ -5244,20 +5256,29 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); + if (info->ChipFamily >= CHIP_FAMILY_R600) mem_size = INREG(R600_CONFIG_MEMSIZE); else mem_size = INREG(RADEON_CONFIG_MEMSIZE); + if (mem_size == 0) { /* Softboot V_BIOS */ - xf86Int10InfoPtr pInt; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); - pInt = xf86InitInt10 (info->pEnt->index); - if (pInt) { - pInt->num = 0xe6; - xf86ExecX86int10 (pInt); - xf86FreeInt10 (pInt); - } + if (info->IsAtomBios) { + rhdAtomASICInit(info->atomBIOS); + } else { + xf86Int10InfoPtr pInt; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); + pInt = xf86InitInt10 (info->pEnt->index); + if (pInt) { + pInt->num = 0xe6; + xf86ExecX86int10 (pInt); + xf86FreeInt10 (pInt); + } else { + RADEONGetBIOSInitTableOffsets(pScrn); + RADEONPostCardFromBIOSTables(pScrn); + } + } } /* Makes sure the engine is idle before doing anything */ diff --git a/src/radeon_reg.h b/src/radeon_reg.h index c5ab0def..b2d6fd18 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -265,6 +265,7 @@ #define RADEON_BRUSH_Y_X 0x1474 #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) +# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) # define RADEON_BUS_RD_DISCARD_EN (1 << 24) # define RADEON_BUS_RD_ABORT_EN (1 << 25) # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) @@ -1046,10 +1047,12 @@ # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_LCD_GPIO_MASK 0x01a0 +#define RADEON_GPIOPAD_EN 0x01a0 #define RADEON_LCD_GPIO_Y_REG 0x01a4 #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_GPIOPAD_MASK 0x0198 #define RADEON_GPIOPAD_A 0x019c #define RADEON_MDGPIO_Y_REG 0x01b4 #define RADEON_MEM_ADDR_CONFIG 0x0148 @@ -1084,6 +1087,9 @@ #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define RADEON_SEPROM_CNTL1 0x01c0 +# define RADEON_SCK_PRESCALE_SHIFT 24 +# define RADEON_SCK_PRESCALE_MASK (0xff << 24) #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f # define R300_MC_IND_WR_EN (1 << 8) @@ -1648,6 +1654,7 @@ # define RADEON_VIP_BUSY 0 # define RADEON_VIP_IDLE 1 # define RADEON_VIP_RESET 2 +# define RADEON_VIPH_EN (1 << 21) #define RADEON_VIPH_DV_LAT 0x0c44 #define RADEON_VIPH_BM_CHUNK 0x0c48 #define RADEON_VIPH_DV_INT 0x0c4c @@ -3435,6 +3442,8 @@ #define AVIVO_HDP_FB_LOCATION 0x134 +#define AVIVO_VGA_RENDER_CONTROL 0x0300 +# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) #define AVIVO_D1VGA_CONTROL 0x0330 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) @@ -3875,6 +3884,15 @@ # define AVIVO_I2C_EN (1 << 0) # define AVIVO_I2C_RESET (1 << 8) +#define R600_GENERAL_PWRMGT 0x618 +# define R600_OPEN_DRAIN_PADS (1 << 11) + +#define R600_LOWER_GPIO_ENABLE 0x710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 + #define R600_MC_VM_FB_LOCATION 0x2180 #define R600_MC_VM_AGP_TOP 0x2184 #define R600_MC_VM_AGP_BOT 0x2188 @@ -3891,6 +3909,11 @@ #define R600_CONFIG_F0_BASE 0x542C #define R600_CONFIG_APER_SIZE 0x5430 +#define R600_ROM_CNTL 0x1600 +# define R600_SCK_OVERWRITE (1 << 1) +# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 +# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) + #define R600_BIOS_0_SCRATCH 0x1724 #define R600_BIOS_1_SCRATCH 0x1728 #define R600_BIOS_2_SCRATCH 0x172c |