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-rw-r--r--man/radeon.man13
-rw-r--r--src/radeon.h7
-rw-r--r--src/radeon_crtc.c25
-rw-r--r--src/radeon_display.c6
-rw-r--r--src/radeon_driver.c20
-rw-r--r--src/radeon_output.c141
-rw-r--r--src/radeon_reg.h9
-rw-r--r--src/radeon_tv.c81
-rw-r--r--src/radeon_video.c233
-rw-r--r--src/radeon_video.h6
10 files changed, 327 insertions, 214 deletions
diff --git a/man/radeon.man b/man/radeon.man
index 2f46c44a..8423cc9b 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -363,13 +363,6 @@ life by reducing power usage. Some users report reduced 3D performance
with this enabled. The default is
.B off.
.TP
-.BI "Option \*qBIOSHotkeys\*q \*q" boolean \*q
-Enable BIOS hotkey output switching. This allows the BIOS to toggle outputs
-using hotkeys (e.g., fn-f7, etc.). Since the driver does not support ACPI,
-there is no way to validate modes on an output switch and the BIOS can
-potentially change things behind the driver's back. The default is
-.B off.
-.TP
.BI "Option \*qVGAAccess\*q \*q" boolean \*q
Tell the driver if it can do legacy VGA IOs to the card. This is
necessary for properly resuming consoles when in VGA text mode, but
@@ -406,6 +399,12 @@ for RN50/ES1000 and
.B on
for others.
.TP
+.BI "Option \*qDefaultConnectorTable\*q \*q" boolean \*q
+Enable this option to skip the BIOS connector table parsing and use the
+driver defaults for each chip.
+The default is
+.B off
+.TP
.SH SEE ALSO
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
diff --git a/src/radeon.h b/src/radeon.h
index aee4c3ec..61283453 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -151,7 +151,8 @@ typedef enum {
OPTION_ACCELMETHOD,
OPTION_CONSTANTDPI,
OPTION_CONNECTORTABLE,
- OPTION_DRI
+ OPTION_DRI,
+ OPTION_DEFAULT_CONNECTOR_TABLE
} RADEONOpts;
@@ -329,6 +330,7 @@ typedef struct {
CARD32 tv_data_delay_b;
CARD32 tv_dac_cntl;
CARD32 tv_pll_cntl;
+ CARD32 tv_pll_cntl1;
CARD32 tv_pll_fine_cntl;
CARD32 tv_modulator_cntl1;
CARD32 tv_modulator_cntl2;
@@ -460,7 +462,6 @@ typedef struct {
Bool IsMobility; /* Mobile chips for laptops */
Bool IsIGP; /* IGP chips */
Bool HasSingleDAC; /* only TVDAC on chip */
- Bool OverlayOnCRTC2;
Bool ddc_mode; /* Validate mode by matching exactly
* the modes supported in DDC data
*/
@@ -947,8 +948,6 @@ void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
void
RADEONEnableOutputs(ScrnInfoPtr pScrn, int crtc_num);
-void
-RADEONChooseOverlayCRTC(ScrnInfoPtr pScrn, BoxPtr dstBox);
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, xf86OutputPtr output);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 8e713302..434034c1 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -1296,28 +1296,3 @@ RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode)
return pMode;
}
-void
-RADEONChooseOverlayCRTC(ScrnInfoPtr pScrn, BoxPtr dstBox)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int c;
- int crtc_num = 0;
-
- for (c = 0; c < xf86_config->num_crtc; c++)
- {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
-
- if (!crtc->enabled)
- continue;
-
- if ((dstBox->x1 >= crtc->x) && (dstBox->y1 >= crtc->y))
- crtc_num = c;
- }
-
- if (crtc_num == 1)
- info->OverlayOnCRTC2 = TRUE;
- else
- info->OverlayOnCRTC2 = FALSE;
-}
-
diff --git a/src/radeon_display.c b/src/radeon_display.c
index e76ffa44..c51fb5de 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -368,6 +368,9 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
} else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp |= RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
}
} else {
@@ -422,6 +425,9 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp &= ~RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
}
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index f338d166..0dc8d566 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -188,6 +188,7 @@ static const OptionInfoRec RADEONOptions[] = {
{ OPTION_CONSTANTDPI, "ConstantDPI", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE },
+ { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -4402,15 +4403,6 @@ static void RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore
hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
- OUTREG(RADEON_TV_MASTER_CNTL, (RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX
- | RADEON_CRT_FIFO_CE_EN
- | RADEON_TV_FIFO_CE_EN
- | RADEON_TV_ON));
-
- /*OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl | RADEON_TV_ON);*/
-
for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) {
tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]);
RADEONWriteTVFIFO(pScrn, hTable, tmp);
@@ -4510,12 +4502,9 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
ErrorF("Entering Restore TV\n");
- OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl | RADEON_TV_ON);
-
OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
| RADEON_TV_ASYNC_RST
| RADEON_CRT_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX
| RADEON_TV_FIFO_ASYNC_RST));
/* Temporarily turn the TV DAC off */
@@ -4533,8 +4522,7 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
| RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX));
+ | RADEON_CRT_ASYNC_RST));
ErrorF("Restore TV Restarts\n");
RADEONRestoreTVRestarts(pScrn, restore);
@@ -4544,8 +4532,7 @@ void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
- | RADEON_TV_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX));
+ | RADEON_TV_ASYNC_RST));
ErrorF("Restore TV standard\n");
RADEONRestoreTVOutputStd(pScrn, restore);
@@ -5304,6 +5291,7 @@ static void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->tv_y_saw_tooth_cntl = INREG(RADEON_TV_Y_SAW_TOOTH_CNTL);
save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL);
+ save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1);
ErrorF("Save TV timing tables\n");
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 73e44f32..9650a397 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2344,34 +2344,29 @@ void RADEONInitConnector(xf86OutputPtr output)
}
-/*
- * initialise the static data sos we don't have to re-do at randr change */
-Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- xf86OutputPtr output;
- char *optstr;
- int i = 0;
- int num_vga = 0;
- int num_dvi = 0;
- /* We first get the information about all connectors from BIOS.
- * This is how the card is phyiscally wired up.
- * The information should be correct even on a OEM card.
- * If not, we may have problem -- need to use MonitorLayout option.
- */
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- info->BiosConnector[i].valid = FALSE;
- info->BiosConnector[i].DDCType = DDC_NONE_DETECTED;
- info->BiosConnector[i].DACType = DAC_UNKNOWN;
- info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
- info->BiosConnector[i].ConnectorType = CONNECTOR_NONE;
- }
+ if (info->IsMobility) {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ info->BiosConnector[0].DDCType = DDC_LCD;
+ info->BiosConnector[0].DACType = DAC_UNKNOWN;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY;
+ info->BiosConnector[0].valid = TRUE;
- if (!RADEONGetConnectorInfoFromBIOS(pScrn)) {
- if (info->IsMobility) {
- /* Below is the most common setting, but may not be true */
+ /* IGP only has TVDAC */
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[1].DDCType = DDC_CRT2;
+ else
+ info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].valid = TRUE;
+ } else {
#if defined(__powerpc__)
info->BiosConnector[0].DDCType = DDC_DVI;
#else
@@ -2387,9 +2382,28 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].TMDSType = TMDS_EXT;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
info->BiosConnector[1].valid = TRUE;
+ }
+ } else {
+ /* Below is the most common setting, but may not be true */
+ if (info->IsIGP) {
+ if (info->ChipFamily == CHIP_FAMILY_RS400)
+ info->BiosConnector[0].DDCType = DDC_CRT2;
+ else
+ info->BiosConnector[0].DDCType = DDC_VGA;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].valid = TRUE;
+ /* not sure what a good default DDCType for DVI on
+ * IGP desktop chips is
+ */
+ info->BiosConnector[1].DDCType = DDC_MONID; /* DDC_DVI? */
+ info->BiosConnector[1].DACType = DAC_UNKNOWN;
+ info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[1].valid = TRUE;
} else {
- /* Below is the most common setting, but may not be true */
info->BiosConnector[0].DDCType = DDC_DVI;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_INT;
@@ -2402,35 +2416,68 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
info->BiosConnector[1].valid = TRUE;
}
+ }
- if (info->InternalTVOut) {
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
- info->BiosConnector[2].valid = TRUE;
- }
+ if (info->InternalTVOut) {
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].valid = TRUE;
+ }
- /* Some cards have the DDC lines swapped and we have no way to
- * detect it yet (Mac cards)
- */
- if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
- info->BiosConnector[0].DDCType = DDC_VGA;
- info->BiosConnector[1].DDCType = DDC_DVI;
- }
+ /* Some cards have the DDC lines swapped and we have no way to
+ * detect it yet (Mac cards)
+ */
+ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
+ info->BiosConnector[0].DDCType = DDC_VGA;
+ info->BiosConnector[1].DDCType = DDC_DVI;
+ }
+
+}
+
+/*
+ * initialise the static data sos we don't have to re-do at randr change */
+Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ xf86OutputPtr output;
+ char *optstr;
+ int i = 0;
+ int num_vga = 0;
+ int num_dvi = 0;
+
+ /* We first get the information about all connectors from BIOS.
+ * This is how the card is phyiscally wired up.
+ * The information should be correct even on a OEM card.
+ */
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ info->BiosConnector[i].valid = FALSE;
+ info->BiosConnector[i].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[i].DACType = DAC_UNKNOWN;
+ info->BiosConnector[i].TMDSType = TMDS_UNKNOWN;
+ info->BiosConnector[i].ConnectorType = CONNECTOR_NONE;
+ }
+
+ if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_CONNECTOR_TABLE, FALSE)) {
+ RADEONSetupGenericConnectors(pScrn);
+ } else {
+ if (!RADEONGetConnectorInfoFromBIOS(pScrn))
+ RADEONSetupGenericConnectors(pScrn);
}
if (info->HasSingleDAC) {
/* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
- if (info->BiosConnector[0].ConnectorType == CONNECTOR_CRT) {
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[1].DACType = DAC_NONE;
- } else {
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[0].DACType = DAC_NONE;
- }
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT)
+ info->BiosConnector[i].DACType = DAC_TVDAC;
+ }
} else if (!pRADEONEnt->HasCRTC2) {
- info->BiosConnector[0].DACType = DAC_PRIMARY;
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT)
+ info->BiosConnector[i].DACType = DAC_PRIMARY;
+ }
}
/* parse connector table option */
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 4e4d8742..9eae40dc 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3141,6 +3141,8 @@
# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
+# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
+# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
# define RADEON_TVOUT_SCALE_EN (1 << 26)
#define RADEON_TV_SYNC_CNTL 0x0808
# define RADEON_SYNC_OE (1 << 0)
@@ -3211,6 +3213,9 @@
# define RADEON_SLEW_RATE_LIMIT (1 << 23)
# define RADEON_CY_FILT_BLEND_SHIFT 28
#define RADEON_TV_MODULATOR_CNTL2 0x0874
+# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
+# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
+# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
#define RADEON_TV_CRC_CNTL 0x0890
#define RADEON_TV_UV_ADR 0x08ac
# define RADEON_MAX_UV_ADR_MASK 0x000000ff
@@ -3242,6 +3247,10 @@
# define RADEON_TVPLL_RESET (1 << 1)
# define RADEON_TVPLL_SLEEP (1 << 3)
# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
+# define RADEON_TVPCP_SHIFT 8
+# define RADEON_TVPCP_MASK (7 << 8)
+# define RADEON_TVPVG_SHIFT 11
+# define RADEON_TVPVG_MASK (7 << 11)
# define RADEON_TVPDC_SHIFT 14
# define RADEON_TVPDC_MASK (3 << 14)
# define RADEON_TVPLL_TEST_DIS (1 << 31)
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index db5288a7..522f7eda 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -205,8 +205,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
@@ -257,7 +256,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
*/
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M||
+ radeon_output->tvStd == TV_STD_PAL_M ||
radeon_output->tvStd == TV_STD_PAL_60)
vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(NTSC_TV_LINES_PER_FRAME);
else
@@ -280,8 +279,7 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
/* Compute H_INC from hSize */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) /
(radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
else
@@ -314,8 +312,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
@@ -332,32 +329,40 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_linear_gain_settings = (0x100 << RADEON_UV_GAIN_SHIFT) |
(0x100 << RADEON_Y_GAIN_SHIFT);
- save->tv_master_cntl = (RADEON_RESTART_PHASE_FIX
- | RADEON_VIN_ASYNC_RST
- | RADEON_AUD_ASYNC_RST
- | RADEON_DVS_ASYNC_RST
+ save->tv_master_cntl = (RADEON_VIN_ASYNC_RST
| RADEON_CRT_FIFO_CE_EN
| RADEON_TV_FIFO_CE_EN
| RADEON_TV_ON);
+ if (!IS_R300_VARIANT)
+ save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
+
+ if (radeon_output->tvStd == TV_STD_NTSC ||
+ radeon_output->tvStd == TV_STD_NTSC_J)
+ save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
+
save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT
| RADEON_SYNC_TIP_LEVEL
| RADEON_YFLT_EN
| RADEON_UVFLT_EN
- | (0x3b << RADEON_BLANK_LEVEL_SHIFT)
- | (0x6 << RADEON_CY_FILT_BLEND_SHIFT);
+ | (2 << RADEON_CY_FILT_BLEND_SHIFT);
if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60 ||
- radeon_output->tvStd == TV_STD_SCART_PAL) {
- save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT);
- save->tv_modulator_cntl2 = 0x00000191;
+ radeon_output->tvStd == TV_STD_NTSC_J) {
+ save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT)
+ | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+ save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+ } else if (radeon_output->tvStd == TV_STD_SCART_PAL) {
+ save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
+ save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
} else {
save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN
- | (0x3b << RADEON_SET_UP_LEVEL_SHIFT);
- save->tv_modulator_cntl2 = 0x003e01b2;
+ | (0x3b << RADEON_SET_UP_LEVEL_SHIFT)
+ | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
+ save->tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
+ ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
}
save->pll_test_cntl = 0;
@@ -367,8 +372,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
| RADEON_CMP_BLU_EN
| RADEON_DAC_DITHER_EN);
- save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN | RADEON_TVOUT_SCALE_EN
- | (0x0b << 16) | (0x07 << 20));
+ save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
+ | RADEON_TVOUT_SCALE_EN
+ | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
+ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT));
if (IsPrimary) {
if (radeon_output->Flags & RADEON_USE_RMX)
@@ -442,9 +449,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_dac_cntl = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | (8 << 16) | (6 << 20);
if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_NTSC_J)
save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
else
save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
@@ -465,9 +470,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
#endif
if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_NTSC_J)
save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) |
(((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
@@ -480,6 +483,12 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
(((PAL_TV_PLL_N >> 8) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
+ save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
+ ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
+ ((1 & RADEON_TVPDC_MASK)<< RADEON_TVPDC_SHIFT) |
+ RADEON_TVCLK_SRC_SEL_TVPLL |
+ RADEON_TVPLL_TEST_DIS);
+
save->tv_upsamp_and_gain_cntl = RADEON_YUPSAMP_EN | RADEON_UVUPSAMP_EN;
save->tv_uv_adr = 0xc8;
@@ -592,8 +601,7 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
@@ -612,7 +620,6 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
- save->disp_merge_cntl |= RADEON_DISP_RGB_OFFSET_EN;
}
void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -625,8 +632,7 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
@@ -679,8 +685,7 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
@@ -699,7 +704,6 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
- save->disp2_merge_cntl |= RADEON_DISP2_RGB_OFFSET_EN;
}
void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -712,8 +716,7 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ radeon_output->tvStd == TV_STD_PAL_M)
constPtr = &availableTVModes[0];
else
constPtr = &availableTVModes[1];
diff --git a/src/radeon_video.c b/src/radeon_video.c
index dbf66dac..a38931c8 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -106,7 +106,7 @@ static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer;
static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity;
static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults;
static Atom xvGamma, xvColorspace;
-static Atom xvSwitchCRT;
+static Atom xvCRTC;
static Atom xvEncoding, xvFrequency, xvVolume, xvMute,
xvDecBrightness, xvDecContrast, xvDecHue, xvDecColor, xvDecSaturation,
xvTunerStatus, xvSAP, xvOverlayDeinterlacingMethod,
@@ -119,6 +119,114 @@ static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode;
#define GET_PORT_PRIVATE(pScrn) \
(RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
+static void
+radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b)
+{
+ dest->x1 = a->x1 > b->x1 ? a->x1 : b->x1;
+ dest->x2 = a->x2 < b->x2 ? a->x2 : b->x2;
+ dest->y1 = a->y1 > b->y1 ? a->y1 : b->y1;
+ dest->y2 = a->y2 < b->y2 ? a->y2 : b->y2;
+
+ if (dest->x1 >= dest->x2 || dest->y1 >= dest->y2)
+ dest->x1 = dest->x2 = dest->y1 = dest->y2 = 0;
+}
+
+static void
+radeon_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box)
+{
+ if (crtc->enabled) {
+ crtc_box->x1 = crtc->x;
+ crtc_box->x2 = crtc->x + xf86ModeWidth(&crtc->mode, crtc->rotation);
+ crtc_box->y1 = crtc->y;
+ crtc_box->y2 = crtc->y + xf86ModeHeight(&crtc->mode, crtc->rotation);
+ } else
+ crtc_box->x1 = crtc_box->x2 = crtc_box->y1 = crtc_box->y2 = 0;
+}
+
+static int
+radeon_box_area(BoxPtr box)
+{
+ return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1);
+}
+
+static xf86CrtcPtr
+radeon_covering_crtc(ScrnInfoPtr pScrn,
+ BoxPtr box,
+ xf86CrtcPtr desired,
+ BoxPtr crtc_box_ret)
+{
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ xf86CrtcPtr crtc, best_crtc;
+ int coverage, best_coverage;
+ int c;
+ BoxRec crtc_box, cover_box;
+
+ best_crtc = NULL;
+ best_coverage = 0;
+ crtc_box_ret->x1 = 0;
+ crtc_box_ret->x2 = 0;
+ crtc_box_ret->y1 = 0;
+ crtc_box_ret->y2 = 0;
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ crtc = xf86_config->crtc[c];
+ radeon_crtc_box(crtc, &crtc_box);
+ radeon_box_intersect(&cover_box, &crtc_box, box);
+ coverage = radeon_box_area(&cover_box);
+ if (coverage && crtc == desired) {
+ *crtc_box_ret = crtc_box;
+ return crtc;
+ } else if (coverage > best_coverage) {
+ *crtc_box_ret = crtc_box;
+ best_crtc = crtc;
+ best_coverage = coverage;
+ }
+ }
+ return best_crtc;
+}
+
+static Bool
+radeon_clip_video_helper(ScrnInfoPtr pScrn,
+ xf86CrtcPtr *crtc_ret,
+ xf86CrtcPtr desired_crtc,
+ BoxPtr dst,
+ INT32 *xa,
+ INT32 *xb,
+ INT32 *ya,
+ INT32 *yb,
+ RegionPtr reg,
+ INT32 width,
+ INT32 height)
+{
+ Bool ret;
+ RegionRec crtc_region_local;
+ RegionPtr crtc_region = reg;
+
+ /*
+ * For overlay video, compute the relevant CRTC and
+ * clip video to that
+ */
+ if (crtc_ret) {
+ BoxRec crtc_box;
+ xf86CrtcPtr crtc = radeon_covering_crtc(pScrn, dst,
+ desired_crtc,
+ &crtc_box);
+
+ if (crtc) {
+ REGION_INIT (pScreen, &crtc_region_local, &crtc_box, 1);
+ crtc_region = &crtc_region_local;
+ REGION_INTERSECT (pScreen, crtc_region, crtc_region, reg);
+ }
+ *crtc_ret = crtc;
+ }
+
+ ret = xf86XVClipVideoHelper(dst, xa, xb, ya, yb,
+ crtc_region, width, height);
+
+ if (crtc_region != reg)
+ REGION_UNINIT (pScreen, &crtc_region_local);
+
+ return ret;
+}
#ifdef USE_EXA
static void
@@ -226,7 +334,7 @@ static XF86AttributeRec Attributes[NUM_ATTRIBUTES] =
{XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"},
{XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"},
{XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"},
- {XvSettable | XvGettable, 0, 1, "XV_SWITCHCRT"},
+ {XvSettable | XvGettable, -1, 1, "XV_CRTC"},
{XvSettable | XvGettable, 100, 10000, "XV_GAMMA"},
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
};
@@ -257,7 +365,7 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] =
{XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"},
{XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"},
{XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"},
- {XvSettable | XvGettable, 0, 1, "XV_SWITCHCRT"},
+ {XvSettable | XvGettable, -1, 1, "XV_CRTC"},
{XvSettable | XvGettable, 100, 10000, "XV_GAMMA"},
{XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
@@ -1082,7 +1190,7 @@ RADEONResetVideo(ScrnInfoPtr pScrn)
xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY");
xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS");
- xvSwitchCRT = MAKE_ATOM("XV_SWITCHCRT");
+ xvCRTC = MAKE_ATOM("XV_CRTC");
xvOvAlpha = MAKE_ATOM("XV_OVERLAY_ALPHA");
xvGrAlpha = MAKE_ATOM("XV_GRAPHICS_ALPHA");
@@ -1295,11 +1403,8 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
pPriv->currentBuffer = 0;
pPriv->autopaint_colorkey = TRUE;
pPriv->gamma = 1000;
- if (info->OverlayOnCRTC2)
- pPriv->crt2 = TRUE;
- else
- pPriv->crt2 = FALSE;
-
+ pPriv->desired_crtc = NULL;
+
pPriv->ov_alpha = 255;
pPriv->gr_alpha = 255;
pPriv->alpha_mode = 0;
@@ -1324,24 +1429,14 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
* 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
* for higher clocks, sure makes life nicer
*/
+ dot_clock = info->ModeReg.dot_clock_freq;
- /* Figure out which head we are on */
- if (info->OverlayOnCRTC2)
- dot_clock = info->ModeReg.dot_clock_freq_2;
- else
- dot_clock = info->ModeReg.dot_clock_freq;
-
- if(dot_clock < 17500)
+ if (dot_clock < 17500)
info->ecp_div = 0;
else
info->ecp_div = 1;
ecp = (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (info->ecp_div << 8);
-#if 0
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dotclock is %g Mhz, setting ecp_div to %d\n", info->ModeReg.dot_clock_freq/100.0, info->ecp_div);
-#endif
-
-
if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200) ||
(info->ChipFamily == CHIP_FAMILY_RS300)) {
@@ -1353,7 +1448,6 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, ecp);
-
/* Decide on tuner type */
if((info->tunerType<0) && (info->MM_TABLE_valid)) {
pPriv->tuner_type = info->MM_TABLE.tuner_type;
@@ -1657,14 +1751,15 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn,
RADEONSetColorKey (pScrn, pPriv->colorKey);
REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
}
- else if(attribute == xvSwitchCRT)
+ else if(attribute == xvCRTC)
{
- pPriv->crt2 = ClipValue (value, 0, 1);
- pPriv->crt2 = value;
- if (pPriv->crt2)
- info->OverlayOnCRTC2 = TRUE;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ if ((value < -1) || (value > xf86_config->num_crtc))
+ return BadValue;
+ if (value < 0)
+ pPriv->desired_crtc = NULL;
else
- info->OverlayOnCRTC2 = FALSE;
+ pPriv->desired_crtc = xf86_config->crtc[value];
}
else if(attribute == xvOvAlpha)
{
@@ -1854,8 +1949,16 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn,
*value = pPriv->doubleBuffer ? 1 : 0;
else if(attribute == xvColorKey)
*value = pPriv->colorKey;
- else if(attribute == xvSwitchCRT)
- *value = pPriv->crt2 ? 1 : 0;
+ else if(attribute == xvCRTC) {
+ int c;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ for (c = 0; c < xf86_config->num_crtc; c++)
+ if (xf86_config->crtc[c] == pPriv->desired_crtc)
+ break;
+ if (c == xf86_config->num_crtc)
+ c = -1;
+ *value = c;
+ }
else if(attribute == xvOvAlpha)
*value = pPriv->ov_alpha;
else if(attribute == xvGrAlpha)
@@ -2388,7 +2491,8 @@ RADEONFreeMemory(
static void
RADEONDisplayVideo(
ScrnInfoPtr pScrn,
- RADEONPortPrivPtr pPriv,
+ xf86CrtcPtr crtc,
+ RADEONPortPrivPtr pPriv,
int id,
int offset1, int offset2,
int offset3, int offset4,
@@ -2425,10 +2529,10 @@ RADEONDisplayVideo(
int predownscale=0;
int src_w_d;
int leftuv = 0;
- xf86CrtcPtr crtc;
DisplayModePtr mode;
RADEONOutputPrivatePtr radeon_output;
xf86OutputPtr output;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
is_rgb=0; is_planar=0;
switch(id){
@@ -2451,7 +2555,7 @@ RADEONDisplayVideo(
workarounds for chip erratas */
/* Figure out which head we are on for dot clock */
- if (info->OverlayOnCRTC2)
+ if (radeon_crtc->crtc_id == 1)
dot_clock = info->ModeReg.dot_clock_freq_2;
else
dot_clock = info->ModeReg.dot_clock_freq;
@@ -2476,11 +2580,6 @@ RADEONDisplayVideo(
v_inc_shift = 20;
y_mult = 1;
- if (info->OverlayOnCRTC2)
- crtc = xf86_config->crtc[1];
- else
- crtc = xf86_config->crtc[0];
-
mode = &crtc->mode;
if (mode->Flags & V_INTERLACE)
@@ -2494,6 +2593,7 @@ RADEONDisplayVideo(
output = xf86_config->output[i];
if (output->crtc == crtc) {
radeon_output = output->driver_private;
+ break;
}
}
@@ -2653,7 +2753,7 @@ RADEONDisplayVideo(
* rendering for the second head.
*/
- if (info->OverlayOnCRTC2) {
+ if (radeon_crtc->crtc_id == 1) {
x_off = 0;
OUTREG(RADEON_OV1_Y_X_START, ((dstBox->x1 + x_off) |
((dstBox->y1*y_mult) << 16)));
@@ -2731,6 +2831,7 @@ RADEONDisplayVideo(
| ((info->ChipFamily >= CHIP_FAMILY_R200) ? RADEON_SCALER_TEMPORAL_DEINT : 0);
break;
}
+
OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl);
OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0);
}
@@ -2804,16 +2905,10 @@ RADEONPutImage(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- RADEONChooseOverlayCRTC(pScrn, &dstBox);
-
- if(!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
- return Success;
-
- if (info->OverlayOnCRTC2)
- crtc = xf86_config->crtc[1];
- else
- crtc = xf86_config->crtc[0];
+ if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
+ return Success;
dstBox.x1 -= crtc->x;
dstBox.x2 -= crtc->x;
@@ -2942,7 +3037,7 @@ RADEONPutImage(
/* FIXME: someone should look at these offsets, I don't think it makes sense how
they are handled throughout the source. */
- RADEONDisplayVideo(pScrn, pPriv, id, offset, offset + d2line, offset + d3line,
+ RADEONDisplayVideo(pScrn, crtc, pPriv, id, offset, offset + d2line, offset + d3line,
offset, offset + d2line, offset + d3line, width, height, dstPitch,
xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
@@ -3183,17 +3278,11 @@ RADEONDisplaySurface(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- RADEONChooseOverlayCRTC(pScrn, &dstBox);
-
- if (!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes,
- surface->width, surface->height))
- return Success;
+ if (!radeon_clip_video_helper(pScrn, &crtc, portPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
+ surface->width, surface->height))
+ return Success;
- if (info->OverlayOnCRTC2)
- crtc = xf86_config->crtc[1];
- else
- crtc = xf86_config->crtc[0];
-
dstBox.x1 -= crtc->x;
dstBox.x2 -= crtc->x;
dstBox.y1 -= crtc->y;
@@ -3203,7 +3292,7 @@ RADEONDisplaySurface(
/* this isn't needed */
RADEONResetVideo(pScrn);
#endif
- RADEONDisplayVideo(pScrn, portPriv, surface->id,
+ RADEONDisplayVideo(pScrn, crtc, portPriv, surface->id,
surface->offsets[0], surface->offsets[0],
surface->offsets[0], surface->offsets[0],
surface->offsets[0], surface->offsets[0],
@@ -3283,6 +3372,7 @@ RADEONPutVideo(
int mult;
int vbi_line_width, vbi_start, vbi_end;
xf86CrtcPtr crtc;
+ RADEONCrtcPrivatePtr radeon_crtc;
RADEON_SYNC(info, pScrn);
/*
@@ -3320,19 +3410,14 @@ RADEONPutVideo(
vbi_line_width = 798*2;
if(width<=640)
- vbi_line_width = 0x640; /* 1600 actually */
- else
- vbi_line_width = 2000; /* might need adjustment */
-
- RADEONChooseOverlayCRTC(pScrn, &dstBox);
-
- if(!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes, width, height))
- return Success;
-
- if (info->OverlayOnCRTC2)
- crtc = xf86_config->crtc[1];
+ vbi_line_width = 0x640; /* 1600 actually */
else
- crtc = xf86_config->crtc[0];
+ vbi_line_width = 2000; /* might need adjustment */
+
+ if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
+ return Success;
dstBox.x1 -= crtc->x;
dstBox.x2 -= crtc->x;
@@ -3487,7 +3572,7 @@ RADEONPutVideo(
RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes);
}
- RADEONDisplayVideo(pScrn, pPriv, id, offset1+top*srcPitch, offset2+top*srcPitch,
+ RADEONDisplayVideo(pScrn, crtc, pPriv, id, offset1+top*srcPitch, offset2+top*srcPitch,
offset3+top*srcPitch, offset4+top*srcPitch, offset1+top*srcPitch,
offset2+top*srcPitch, width, height, dstPitch*mult/2,
xa, xb, ya, &dstBox, src_w, src_h*mult/2, drw_w, drw_h, pPriv->overlay_deinterlacing_method);
diff --git a/src/radeon_video.h b/src/radeon_video.h
index b6d5d2d9..072f40e1 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -11,6 +11,8 @@
#include "generic_bus.h"
#include "theatre.h"
+#include "xf86Crtc.h"
+
/* Xvideo port struct */
typedef struct {
CARD32 transform_index;
@@ -40,7 +42,7 @@ typedef struct {
CARD8 tuner_type;
MSP3430Ptr msp3430;
TDA9885Ptr tda9885;
- UDA1380Ptr uda1380;
+ UDA1380Ptr uda1380;
/* VIP bus and devices */
GENERIC_BUS_Ptr VIP;
@@ -77,7 +79,7 @@ typedef struct {
Time offTime;
Time freeTime;
Bool autopaint_colorkey;
- Bool crt2; /* 0=CRT1, 1=CRT2 */
+ xf86CrtcPtr desired_crtc;
#ifdef USE_EXA
int size;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 15:17:59 +0000