summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/atombios_crtc.c11
-rw-r--r--src/legacy_crtc.c43
-rw-r--r--src/radeon_crtc.c51
3 files changed, 85 insertions, 20 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 7a2e378b..93bf94fa 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -492,16 +492,15 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
- OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + mode->HDisplay);
- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + mode->VDisplay);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
- OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
- mode->VDisplay);
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
(mode->HDisplay << 16) | mode->VDisplay);
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 5ed14d44..78ac5b39 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -103,6 +103,31 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
}
}
+void
+RADEONRestoreCrtcBase(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (IS_R300_VARIANT)
+ OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0);
+ OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
+ OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
+}
+
+void
+RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (IS_R300_VARIANT)
+ OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0);
+ OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
+ OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
+}
/* Write CRTC registers */
void
@@ -133,10 +158,7 @@ RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
- if (IS_R300_VARIANT)
- OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0);
- OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
- OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
+ RADEONRestoreCrtcBase(pScrn, restore);
OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
@@ -180,10 +202,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid);
OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid);
- if (IS_R300_VARIANT)
- OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0);
- OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
- OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
+ RADEONRestoreCrtc2Base(pScrn, restore);
OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
@@ -749,8 +768,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
}
-
-static Bool
+void
RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
int x, int y)
{
@@ -863,8 +881,6 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
#endif
save->crtc_offset = Base;
- return TRUE;
-
}
/* Define CRTC registers for requested video mode */
@@ -968,7 +984,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-static Bool
+void
RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
int x, int y)
{
@@ -1077,7 +1093,6 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
#endif
save->crtc2_offset = Base;
- return TRUE;
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index d764782c..e0875a4e 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -472,6 +472,54 @@ radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data
}
+#if XF86_CRTC_VERSION >= 2
+#include "radeon_atombios.h"
+
+extern AtomBiosResult
+atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock);
+extern void
+RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
+ int x, int y);
+extern void
+RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
+ int x, int y);
+extern void
+RADEONRestoreCrtcBase(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void
+RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+
+static void
+radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (IS_AVIVO_VARIANT) {
+ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ } else {
+ switch (radeon_crtc->crtc_id) {
+ case 0:
+ RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
+ RADEONRestoreCrtcBase(pScrn, info->ModeReg);
+ break;
+ case 1:
+ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
+ RADEONRestoreCrtc2Base(pScrn, info->ModeReg);
+ break;
+ default:
+ break;
+ }
+ }
+}
+#endif
+
+
static xf86CrtcFuncsRec radeon_crtc_funcs = {
.dpms = radeon_crtc_dpms,
.save = NULL, /* XXX */
@@ -492,6 +540,9 @@ static xf86CrtcFuncsRec radeon_crtc_funcs = {
.hide_cursor = radeon_crtc_hide_cursor,
.load_cursor_argb = radeon_crtc_load_cursor_argb,
.destroy = NULL, /* XXX */
+#if XF86_CRTC_VERSION >= 2
+ .set_origin = radeon_crtc_set_origin,
+#endif
};
void
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 21:40:33 +0000