diff options
| -rw-r--r-- | src/radeon.h | 4 | ||||
| -rw-r--r-- | src/radeon_common.h | 2 | ||||
| -rw-r--r-- | src/radeon_dri.c | 30 | ||||
| -rw-r--r-- | src/radeon_dri.h | 2 | ||||
| -rw-r--r-- | src/radeon_driver.c | 24 |
5 files changed, 58 insertions, 4 deletions
diff --git a/src/radeon.h b/src/radeon.h index 814db80a..b1060cdc 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -543,6 +543,9 @@ typedef struct { CARD32 backPitchOffset; CARD32 depthPitchOffset; + int pciGartSize; + CARD32 pciGartOffset; + /* offscreen memory management */ int backLines; FBAreaPtr backArea; @@ -709,6 +712,7 @@ extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); extern void RADEONDRICloseScreen(ScreenPtr pScreen); extern void RADEONDRIResume(ScreenPtr pScreen); extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); +extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); diff --git a/src/radeon_common.h b/src/radeon_common.h index d64c1361..a6d99c80 100644 --- a/src/radeon_common.h +++ b/src/radeon_common.h @@ -473,6 +473,7 @@ typedef struct drm_radeon_set_param { #define RADEON_SETPARAM_FB_LOCATION 1 #define RADEON_SETPARAM_SWITCH_TILING 2 +#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* 1.14: Clients can allocate/free a surface */ @@ -486,5 +487,4 @@ typedef struct drm_radeon_surface_free { unsigned int address; } drmRadeonSurfaceFree; - #endif diff --git a/src/radeon_dri.c b/src/radeon_dri.c index d302f3e1..8e2fe447 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1969,3 +1969,33 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) if (info->cursor_start) xf86ForceHWCursor (pScreen, FALSE); } + +void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + FBAreaPtr fbarea; + int width; + int height; + int width_bytes; + int size_bytes; + + if (!info->IsPCI || info->drmMinor<19) + return; + + size_bytes = RADEON_PCIGART_TABLE_SIZE; + width = pScrn->displayWidth; + width_bytes = width * (pScrn->bitsPerPixel / 8); + height = (size_bytes + width_bytes - 1)/width_bytes; + + fbarea = xf86AllocateOffscreenArea(pScreen, width, height, 256, NULL, NULL, NULL); + + if (!fbarea) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "PCI GART Table allocation failed due to stupid memory manager\n"); + } else { + info->pciGartSize = size_bytes; + info->pciGartOffset = RADEON_ALIGN((fbarea->box.x1 + fbarea->box.y1 * width) * + info->CurrentLayout.pixel_bytes, 256); + + } +} diff --git a/src/radeon_dri.h b/src/radeon_dri.h index 9a90ec84..c93bc4ed 100644 --- a/src/radeon_dri.h +++ b/src/radeon_dri.h @@ -54,6 +54,8 @@ #define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ +#define RADEON_PCIGART_TABLE_SIZE 32768 + #define RADEON_AGP_MAX_MODE 8 #define RADEON_CARD_TYPE_RADEON 1 diff --git a/src/radeon_driver.c b/src/radeon_driver.c index eb3b7a8e..b49b962d 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -5299,10 +5299,10 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; } /* If there's still no space for textures, try without pixmap cache, but never use - the reserved space and the space hw cursor might use */ + the reserved space, the space hw cursor and PCIGART table might use */ if (info->textureSize < 0) { info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize - - 2 * width_bytes - 16384; + - 2 * width_bytes - 16384 - RADEON_PCIGART_TABLE_SIZE; } /* Check to see if there is more room available after the 8192nd @@ -5420,6 +5420,9 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } else { xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n"); } + + RADEONDRIAllocatePCIGARTTable(pScreen); + if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0)) { xf86DrvMsg(scrnIndex, X_INFO, @@ -5450,6 +5453,9 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "Will use depth buffer at offset 0x%x\n", info->depthOffset); xf86DrvMsg(scrnIndex, X_INFO, + "Will use %d kb for PCI GART table at offset 0x%x\n", + info->pciGartSize/1024, info->pciGartOffset); + xf86DrvMsg(scrnIndex, X_INFO, "Will use %d kb for textures at offset 0x%x\n", info->textureSize/1024, info->textureOffset); @@ -5610,7 +5616,19 @@ _X_EXPORT Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); #ifdef XF86DRI - /* DRI finalization */ + if (info->IsPCI && info->pciGartOffset && info->drmMinor>=19) + { + drmRadeonSetParam radeonsetparam; + memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam)); + radeonsetparam.param = RADEON_SETPARAM_PCIGART_LOCATION; + radeonsetparam.value = info->pciGartOffset; + if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM, + &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[drm] failed set pci gart location\n"); + } + + /* DRI finalization */ if (info->directRenderingEnabled) { /* Now that mi, fb, drm and others have done their thing, complete the DRI |