diff options
| -rw-r--r-- | configure.ac | 2 | ||||
| -rw-r--r-- | src/radeon.h | 16 | ||||
| -rw-r--r-- | src/radeon_accel.c | 38 | ||||
| -rw-r--r-- | src/radeon_bios.c | 18 | ||||
| -rw-r--r-- | src/radeon_commonfuncs.c | 14 | ||||
| -rw-r--r-- | src/radeon_cursor.c | 40 | ||||
| -rw-r--r-- | src/radeon_display.c | 12 | ||||
| -rw-r--r-- | src/radeon_dri.c | 22 | ||||
| -rw-r--r-- | src/radeon_driver.c | 295 | ||||
| -rw-r--r-- | src/radeon_exa.c | 17 | ||||
| -rw-r--r-- | src/radeon_reg.h | 8 |
11 files changed, 302 insertions, 180 deletions
diff --git a/configure.ac b/configure.ac index ddfa7c8e..8b29d8d5 100644 --- a/configure.ac +++ b/configure.ac @@ -22,7 +22,7 @@ AC_PREREQ(2.57) AC_INIT([xf86-video-ati], - 6.6.191, + 6.6.192, [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], xf86-video-ati) diff --git a/src/radeon.h b/src/radeon.h index d75b1547..eb4902bb 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -153,7 +153,6 @@ typedef enum { } RADEONOpts; -#define RADEON_DEBUG 1 /* Turn off debugging output */ #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ @@ -165,15 +164,7 @@ typedef enum { * for something else. */ -#if RADEON_DEBUG -#define RADEONTRACE(x) \ -do { \ - ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \ - ErrorF x; \ -} while(0) -#else -#define RADEONTRACE(x) do { } while(0) -#endif +#define RADEON_LOGLEVEL_DEBUG 4 /* for Xv, outputs */ #define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) @@ -299,6 +290,10 @@ typedef struct { CARD32 tv_dac_cntl; + CARD32 rs480_unk_e30; + CARD32 rs480_unk_e34; + CARD32 rs480_unk_e38; + CARD32 rs480_unk_e3c; } RADEONSaveRec, *RADEONSavePtr; typedef struct { @@ -782,6 +777,7 @@ extern Bool RADEONAccelInit(ScreenPtr pScreen); extern Bool RADEONSetupMemEXA (ScreenPtr pScreen); extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); #ifdef XF86DRI +extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type); extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset); diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 41859c4a..b739988f 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -134,9 +134,10 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; if (info->fifo_slots >= entries) return; } - RADEONTRACE(("FIFO timed out: %u entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "FIFO timed out: %u entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "FIFO timed out, resetting engine...\n"); RADEONEngineReset(pScrn); @@ -165,8 +166,9 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) break; } if (i == RADEON_TIMEOUT) { - RADEONTRACE(("DC flush timeout: %x\n", - INREG(RADEON_RB3D_DSTCACHE_CTLSTAT))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DC flush timeout: %x\n", + INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); } } @@ -296,9 +298,10 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("EngineRestore (%d/%d)\n", - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "EngineRestore (%d/%d)\n", + info->CurrentLayout.pixel_code, + info->CurrentLayout.bitsPerPixel); /* Setup engine location. This shouldn't be necessary since we * set them appropriately before any accel ops, but let's avoid @@ -347,9 +350,10 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("EngineInit (%d/%d)\n", - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "EngineInit (%d/%d)\n", + info->CurrentLayout.pixel_code, + info->CurrentLayout.bitsPerPixel); OUTREG(RADEON_RB3D_CNTL, 0); @@ -362,15 +366,17 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) case 24: info->datatype = 5; break; case 32: info->datatype = 6; break; default: - RADEONTRACE(("Unknown depth/bpp = %d/%d (code = %d)\n", - info->CurrentLayout.depth, - info->CurrentLayout.bitsPerPixel, - info->CurrentLayout.pixel_code)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Unknown depth/bpp = %d/%d (code = %d)\n", + info->CurrentLayout.depth, + info->CurrentLayout.bitsPerPixel, + info->CurrentLayout.pixel_code); } info->pitch = ((info->CurrentLayout.displayWidth / 8) * (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1)); - RADEONTRACE(("Pitch for acceleration = %d\n", info->pitch)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Pitch for acceleration = %d\n", info->pitch); info->dp_gui_master_cntl = ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) diff --git a/src/radeon_bios.c b/src/radeon_bios.c index 25cd1a81..8d5c0ec7 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -34,12 +34,28 @@ #include "xf86.h" #include "xf86_OSproc.h" +#include "xf86PciInfo.h" #include "radeon.h" #include "radeon_reg.h" #include "radeon_macros.h" #include "radeon_probe.h" #include "vbe.h" +int RADEONBIOSApplyConnectorQuirks(ScrnInfoPtr pScrn, int connector_found) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + + /* quirk for compaq nx6125 - the bios lies about the VGA DDC */ + if (info->PciInfo->subsysVendor == PCI_VENDOR_HP) { + if (info->PciInfo->subsysCard == 0x308b) { + if (info->BiosConnector[1].DDCType == DDC_CRT2) + info->BiosConnector[1].DDCType = DDC_MONID; + } + } + return connector_found; +} + /* Read the Video BIOS block and the FP registers (if applicable). */ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { @@ -296,6 +312,8 @@ Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) connector_found = 1; } + connector_found = RADEONBIOSApplyConnectorQuirks(pScrn, connector_found); + if (connector_found == 0) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No connector found in Connector Info Table.\n"); } else { diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index 70f7ddc1..6a999af5 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -156,9 +156,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) #endif #if 0 - RADEONTRACE(("WaitForIdle (entering): %d entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "WaitForIdle (entering): %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); #endif /* Wait for the engine to go idle */ @@ -171,9 +172,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) return; } } - RADEONTRACE(("Idle timed out: %u entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Idle timed out: %u entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Idle timed out, resetting engine...\n"); RADEONEngineReset(pScrn); diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index 68771f8f..67466155 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -70,8 +70,6 @@ static CARD32 mono_cursor_color[] = { #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 -#define COMMON_CURSOR_SWAPPING_START() RADEON_SYNC(info, pScrn) - /* * The cursor bits are always 32bpp. On MSBFirst buses, * configure byte swapping to swap 32 bit units when writing @@ -83,7 +81,6 @@ static CARD32 mono_cursor_color[] = { #define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO; #define CURSOR_SWAPPING_START() \ do { \ - COMMON_CURSOR_SWAPPING_START(); \ OUTREG(RADEON_SURFACE_CNTL, \ (info->ModeReg.surface_cntl | \ RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ @@ -95,10 +92,7 @@ static CARD32 mono_cursor_color[] = { #else #define CURSOR_SWAPPING_DECL_MMIO -#define CURSOR_SWAPPING_START() \ - do { \ - COMMON_CURSOR_SWAPPING_START(); \ - } while (0) +#define CURSOR_SWAPPING_START() #define CURSOR_SWAPPING_END() #endif @@ -112,14 +106,14 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + RADEON_SYNC(info, pScrn); + if (crtc_id == 0) - OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, - ~RADEON_CRTC_CUR_EN); + OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20, + ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); else if (crtc_id == 1) - OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, - ~RADEON_CRTC2_CUR_EN); - - + OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20, + ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK)); } void @@ -131,6 +125,8 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + RADEON_SYNC(info, pScrn); + if (crtc_id == 0) OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN); else if (crtc_id == 1) @@ -277,22 +273,10 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) unsigned char *RADEONMMIO = info->MMIO; CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); int x, y, w, h; - CARD32 save1 = 0; - CARD32 save2 = 0; CARD32 *i; RADEONCTRACE(("RADEONLoadCursorARGB\n")); - if (crtc_id == 0) { - save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); - save1 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN); - } else if (crtc_id == 1) { - save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20); - save2 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN); - } - info->cursor_argb = TRUE; CURSOR_SWAPPING_START(); @@ -323,12 +307,6 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) #endif CURSOR_SWAPPING_END (); - - if (crtc_id == 0) { - OUTREG(RADEON_CRTC_GEN_CNTL, save1); - } else if (crtc_id == 1) { - OUTREG(RADEON_CRTC2_GEN_CNTL, save2); - } } #endif diff --git a/src/radeon_display.c b/src/radeon_display.c index 3bbf3714..0442b9af 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -1340,8 +1340,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph_buffer_cntl, + INREG(RADEON_GRPH_BUFFER_CNTL)); if (mode2) { stop_req = mode2->HDisplay * pixel_bytes2 / 16; @@ -1388,8 +1390,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph2_buffer_cntl, + INREG(RADEON_GRPH2_BUFFER_CNTL)); } } diff --git a/src/radeon_dri.c b/src/radeon_dri.c index b09a8cf4..39393f54 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1475,6 +1475,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->createDummyCtx = TRUE; pDRIInfo->createDummyCtxPriv = FALSE; +#ifdef USE_EXA + if (info->useEXA) { +#if DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3 + int major, minor, patch; + + DRIQueryVersion(&major, &minor, &patch); + + if (minor >= 3) +#endif +#if DRIINFO_MAJOR_VERSION > 5 || \ + (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3) + pDRIInfo->texOffsetStart = RADEONTexOffsetStart; +#endif + } +#endif + if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[dri] DRIScreenInit failed. Disabling DRI.\n"); @@ -1690,7 +1706,8 @@ void RADEONDRIStop(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); RING_LOCALS; - RADEONTRACE(("RADEONDRIStop\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDRIStop\n"); /* Stop the CP */ if (info->directRenderingInited) { @@ -1712,7 +1729,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); drmRadeonInit drmInfo; - RADEONTRACE(("RADEONDRICloseScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDRICloseScreen\n"); if (info->irq) { drmCtlUninstHandler(info->drmFD); diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 42d18997..b3997363 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -590,7 +590,8 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) if (info->FBDev) { info->FB = fbdevHWMapVidmem(pScrn); } else { - RADEONTRACE(("Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); info->FB = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER, info->PciTag, @@ -1249,10 +1250,14 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) */ info->mc_agp_location = 0xffffffc0; - RADEONTRACE(("RADEONInitMemoryMap() : \n")); - RADEONTRACE((" mem_size : 0x%08lx\n", mem_size)); - RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location)); - RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONInitMemoryMap() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " mem_size : 0x%08lx\n", mem_size); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location); } static void RADEONGetVRamType(ScrnInfoPtr pScrn) @@ -1661,7 +1666,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) case PCI_CHIP_RS482_5974: info->ChipFamily = CHIP_FAMILY_RS400; info->IsIGP = TRUE; - info->HasSingleDAC = TRUE; /* ??? */ + info->HasSingleDAC = TRUE; break; case PCI_CHIP_RV410_564A: @@ -2543,7 +2548,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) const char *s; MessageType from; - RADEONTRACE(("RADEONPreInit\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONPreInit\n"); if (pScrn->numEntities != 1) return FALSE; if (!RADEONGetRec(pScrn)) return FALSE; @@ -3315,13 +3321,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, char* s; #endif - #ifdef XF86DRI - RADEONTRACE(("RADEONScreenInit %lx %ld %d\n", - pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit %lx %ld %d\n", + pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); #else - RADEONTRACE(("RADEONScreenInit %lx %ld\n", - pScrn->memPhysBase, pScrn->fbOffset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit %lx %ld\n", + pScrn->memPhysBase, pScrn->fbOffset); #endif info->accelOn = FALSE; @@ -3331,6 +3338,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #ifdef XF86DRI pScrn->fbOffset = info->frontOffset; #endif + if (!RADEONMapMem(pScrn)) return FALSE; #ifdef XF86DRI @@ -3429,12 +3437,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif /* Initial setup of surfaces */ - RADEONTRACE(("Setting up initial surfaces\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up initial surfaces\n"); RADEONChangeSurfaces(pScrn); /* Memory manager setup */ - RADEONTRACE(("Setting up accel memmap\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up accel memmap\n"); #ifdef USE_EXA if (info->useEXA) { @@ -3539,7 +3549,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } #endif - RADEONTRACE(("Initializing fb layer\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing fb layer\n"); /* Init fb layer */ if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, @@ -3615,7 +3626,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); /* Backing store setup */ - RADEONTRACE(("Initializing backing store\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing backing store\n"); miInitializeBackingStore(pScreen); xf86SetBackingStore(pScreen); @@ -3635,7 +3647,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } if (info->directRenderingEnabled) { - RADEONTRACE(("DRI Finishing init !\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DRI Finishing init !\n"); info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); } if (info->directRenderingEnabled) { @@ -3664,12 +3677,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif /* Make sure surfaces are allright since DRI setup may have changed them */ - RADEONTRACE(("Setting up final surfaces\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up final surfaces\n"); + RADEONChangeSurfaces(pScrn); /* Enable aceleration */ if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - RADEONTRACE(("Initializing Acceleration\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Acceleration\n"); if (RADEONAccelInit(pScreen)) { xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); info->accelOn = TRUE; @@ -3685,10 +3701,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } /* Init DPMS */ - RADEONTRACE(("Initializing DPMS\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing DPMS\n"); xf86DPMSInit(pScreen, xf86DPMSSet, 0); - RADEONTRACE(("Initializing Cursor\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Cursor\n"); /* Set Silken Mouse */ xf86SetSilkenMouse(pScreen); @@ -3725,14 +3743,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } - - /* DGA setup */ - RADEONTRACE(("Initializing DGA\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing DGA\n"); RADEONDGAInit(pScreen); /* Init Xv */ - RADEONTRACE(("Initializing Xv\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Xv\n"); RADEONInitVideo(pScreen); /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ @@ -3751,7 +3769,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, pScrn->PointerMoved = RADEONPointerMoved; /* Colormap setup */ - RADEONTRACE(("Initializing color map\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing color map\n"); if (!miCreateDefColormap(pScreen)) return FALSE; if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, RADEONLoadPalette, NULL, @@ -3765,7 +3784,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (serverGeneration == 1) xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); - RADEONTRACE(("RADEONScreenInit finished\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit finished\n"); return TRUE; } @@ -3779,9 +3799,12 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; int timeout; - RADEONTRACE(("RADEONRestoreMemMapRegisters() : \n")); - RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location)); - RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONRestoreMemMapRegisters() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location); /* Write memory mapping registers only if their value change * since we must ensure no access is done while they are @@ -3792,7 +3815,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; CARD32 old_mc_status, status_idle; - RADEONTRACE((" Map Changed ! Applying ...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map Changed ! Applying ...\n"); /* Make sure engine is idle. We assume the CCE is stopped * at this point @@ -3865,7 +3889,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, /* Make sure map fully reached the chip */ (void)INREG(RADEON_MC_FB_LOCATION); - RADEONTRACE((" Map applied, resetting engine ...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map applied, resetting engine ...\n"); /* Reset the engine and HDP */ RADEONEngineReset(pScrn); @@ -3902,7 +3927,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, } } - RADEONTRACE(("Updating display base addresses...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Updating display base addresses...\n"); OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); if (pRADEONEnt->HasCRTC2) @@ -3913,7 +3939,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, /* More paranoia delays, wait 100ms */ usleep(100000); - RADEONTRACE(("Memory map updated.\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Memory map updated.\n"); } #ifdef XF86DRI @@ -4074,8 +4101,9 @@ void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("Programming CRTC1, offset: 0x%08lx\n", - restore->crtc_offset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Programming CRTC1, offset: 0x%08lx\n", + restore->crtc_offset); /* We prevent the CRTC from hitting the memory controller until * fully programmed @@ -4126,8 +4154,9 @@ void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; /* CARD32 crtc2_gen_cntl;*/ - RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n", - restore->crtc2_offset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Programming CRTC2, offset: 0x%08lx\n", + restore->crtc2_offset); /* We prevent the CRTC from hitting the memory controller until * fully programmed @@ -4153,6 +4182,12 @@ void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); + if (info->ChipFamily == CHIP_FAMILY_RS400) { + OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30); + OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34); + OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38); + OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c); + } OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); } @@ -4318,15 +4353,17 @@ void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", - restore->ppll_ref_div, - restore->ppll_div_3, - restore->htotal_cntl, - INPLL(pScrn, RADEON_PPLL_CNTL))); - RADEONTRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", + restore->ppll_ref_div, + restore->ppll_div_3, + restore->htotal_cntl, + INPLL(pScrn, RADEON_PPLL_CNTL)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: rd=%d, fd=%d, pd=%d\n", + restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, + restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, + (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); usleep(50000); /* Let the clock to lock */ @@ -4350,11 +4387,10 @@ void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, OUTPLLP(pScrn, RADEON_P2PLL_CNTL, RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN, + | RADEON_P2PLL_ATOMIC_UPDATE_EN, ~(RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); + | RADEON_P2PLL_ATOMIC_UPDATE_EN)); + OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, restore->p2pll_ref_div, @@ -4377,18 +4413,19 @@ void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 0, ~(RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); - - RADEONTRACE(("Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", - restore->p2pll_ref_div, - restore->p2pll_div_0, - restore->htotal_cntl2, - INPLL(pScrn, RADEON_P2PLL_CNTL))); - RADEONTRACE(("Wrote: rd=%ld, fd=%ld, pd=%ld\n", - restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, - (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16)); + | RADEON_P2PLL_ATOMIC_UPDATE_EN)); + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", + restore->p2pll_ref_div, + restore->p2pll_div_0, + restore->htotal_cntl2, + INPLL(pScrn, RADEON_P2PLL_CNTL)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote2: rd=%ld, fd=%ld, pd=%ld\n", + restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, + restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, + (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16); usleep(5000); /* Let the clock to lock */ @@ -4608,7 +4645,9 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONCrtcPrivatePtr pCRTC1 = pRADEONEnt->Controller[0]; RADEONCrtcPrivatePtr pCRTC2 = pRADEONEnt->Controller[1]; xf86OutputPtr output; - RADEONTRACE(("RADEONRestoreMode(%p)\n", restore)); + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONRestoreMode(%p)\n", restore); /* For Non-dual head card, we don't have private field in the Entity */ if (!pRADEONEnt->HasCRTC2) { @@ -4812,6 +4851,13 @@ static void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); + if (info->ChipFamily == CHIP_FAMILY_RS400) { + save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30); + save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34); + save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38); + save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c); + } + save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } @@ -4823,14 +4869,16 @@ static void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); save->vclk_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08lx\n", - save->ppll_ref_div, - save->ppll_div_3, - save->htotal_cntl)); - RADEONTRACE(("Read: rd=%d, fd=%d, pd=%d\n", - save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: 0x%08x 0x%08x 0x%08lx\n", + save->ppll_ref_div, + save->ppll_div_3, + save->htotal_cntl); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: rd=%d, fd=%d, pd=%d\n", + save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, + save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, + (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); } /* Read PLL registers */ @@ -4841,14 +4889,16 @@ static void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - RADEONTRACE(("Read: 0x%08lx 0x%08lx 0x%08lx\n", - save->p2pll_ref_div, - save->p2pll_div_0, - save->htotal_cntl2)); - RADEONTRACE(("Read: rd=%ld, fd=%ld, pd=%ld\n", - save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, - (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: 0x%08lx 0x%08lx 0x%08lx\n", + save->p2pll_ref_div, + save->p2pll_div_0, + save->htotal_cntl2); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: rd=%ld, fd=%ld, pd=%ld\n", + save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, + save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, + (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16); } /* Read palette data */ @@ -4876,7 +4926,8 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONSaveMode(%p)\n", save)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveMode(%p)\n", save); RADEONSaveMemMapRegisters(pScrn, save); RADEONSaveCommonRegisters(pScrn, save); @@ -4888,7 +4939,8 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONSavePLL2Registers (pScrn, save); /*RADEONSavePalette(pScrn, save);*/ - RADEONTRACE(("RADEONSaveMode returns %p\n", save)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveMode returns %p\n", save); } /* Save everything needed to restore the original VC state */ @@ -4898,7 +4950,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr save = &info->SavedReg; - RADEONTRACE(("RADEONSave\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSave\n"); + if (info->FBDev) { RADEONSaveMemMapRegisters(pScrn, save); fbdevHWSave(pScrn); @@ -4941,7 +4995,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr restore = &info->SavedReg; - RADEONTRACE(("RADEONRestore\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONRestore\n"); #if X_BYTE_ORDER == X_BIG_ENDIAN RADEONWaitForFifo(pScrn, 1); @@ -5061,10 +5116,10 @@ static void RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEON_TV_DAC_GDACPD); } /* FIXME: doesn't make sense, this just replaces the previous value... */ - save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK | + save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | - RADEON_TV_DAC_STD_PS2 | - info->tv_dac_adj); + RADEON_TV_DAC_STD_PS2); + // info->tv_dac_adj); } static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, @@ -5771,6 +5826,13 @@ Bool RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, } #endif + if (info->ChipFamily == CHIP_FAMILY_RS400) { + save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */ + save->rs480_unk_e34 = 0x2749D000; /* AMD really should */ + save->rs480_unk_e38 = 0x29ca71dc; /* release docs */ + save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */ + } + return TRUE; } @@ -5830,11 +5892,12 @@ void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, pll->reference_freq); save->post_div = post_div->divider; - RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", - save->dot_clock_freq, - save->pll_output_freq, - save->feedback_div, - save->post_div)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "dc=%ld, of=%ld, fd=%d, pd=%d\n", + save->dot_clock_freq, + save->pll_output_freq, + save->feedback_div, + save->post_div); save->ppll_ref_div = pll->reference_div; save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); @@ -5897,11 +5960,12 @@ void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, pll->reference_freq); save->post_div_2 = post_div->divider; - RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", - save->dot_clock_freq_2, - save->pll_output_freq_2, - save->feedback_div_2, - save->post_div_2)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "dc=%ld, of=%ld, fd=%d, pd=%d\n", + save->dot_clock_freq_2, + save->pll_output_freq_2, + save->feedback_div_2, + save->post_div_2); save->p2pll_ref_div = pll->reference_div; save->p2pll_div_0 = (save->feedback_div_2 | @@ -5929,7 +5993,8 @@ static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; Bool unblank; - RADEONTRACE(("RADEONSaveScreen(%d)\n", mode)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveScreen(%d)\n", mode); unblank = xf86IsUnblank(mode); if (unblank) SetTimeSinceLastInputEvent(); @@ -5976,7 +6041,8 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) } #endif - RADEONTRACE(("RADEONSwitchMode() !n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSwitchMode() !n"); if (info->allowColorTiling) { info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; @@ -6079,7 +6145,8 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) #endif #if 0 /* Verbose */ - RADEONTRACE(("RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); #endif if (info->showCache && y) { @@ -6228,7 +6295,8 @@ Bool RADEONEnterVT(int scrnIndex, int flags) unsigned char *RADEONMMIO = info->MMIO; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONTRACE(("RADEONEnterVT\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONEnterVT\n"); if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */ xf86Int10InfoPtr pInt; @@ -6319,7 +6387,8 @@ void RADEONLeaveVT(int scrnIndex, int flags) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONSavePtr save = &info->ModeReg; - RADEONTRACE(("RADEONLeaveVT\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { DRILock(pScrn->pScreen, 0); @@ -6356,7 +6425,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) } RADEONRestore(pScrn); - RADEONTRACE(("Ok, leaving now...\n")); + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Ok, leaving now...\n"); } /* Called at the end of each server generation. Restore the original @@ -6368,7 +6439,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONCloseScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONCloseScreen\n"); /* Mark acceleration as stopped or we might try to access the engine at * wrong times, especially if we had DRI, after DRI has been stopped @@ -6400,7 +6472,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) RADEONRestore(pScrn); } - RADEONTRACE(("Disposing accel...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing accel...\n"); #ifdef USE_EXA if (info->exa) { exaDriverFini(pScreen); @@ -6420,14 +6493,17 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) } #endif /* USE_XAA */ - RADEONTRACE(("Disposing cusor info\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing cusor info\n"); if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); info->cursor = NULL; - RADEONTRACE(("Disposing DGA\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing DGA\n"); if (info->DGAModes) xfree(info->DGAModes); info->DGAModes = NULL; - RADEONTRACE(("Unmapping memory\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Unmapping memory\n"); RADEONUnmapMem(pScrn); pScrn->vtSema = FALSE; @@ -6444,7 +6520,8 @@ void RADEONFreeScreen(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONFreeScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONFreeScreen\n"); /* when server quits at PreInit, we don't need do this anymore*/ if (!info) return; diff --git a/src/radeon_exa.c b/src/radeon_exa.c index f9bcaceb..d074f08a 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -496,3 +496,20 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) return TRUE; } + +#ifdef XF86DRI + +#ifndef ExaOffscreenMarkUsed +extern void ExaOffscreenMarkUsed(PixmapPtr); +#endif + +unsigned long long +RADEONTexOffsetStart(PixmapPtr pPix) +{ + exaMoveInPixmap(pPix); + ExaOffscreenMarkUsed(pPix); + + return RADEONPTR(xf86Screens[pPix->drawable.pScreen->myNum])->fbLocation + + exaGetPixmapOffset(pPix); +} +#endif diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 892e8d0b..72470a66 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -308,7 +308,7 @@ # define RADEON_CRTC_CSYNC_EN (1 << 4) # define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) -# define RADEON_CRTC_CUR_MODE_MASK (7 << 17) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) @@ -3130,4 +3130,10 @@ # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) + +#define RADEON_RS480_UNK_e30 0xe30 +#define RADEON_RS480_UNK_e34 0xe34 +#define RADEON_RS480_UNK_e38 0xe38 +#define RADEON_RS480_UNK_e3c 0xe3c + #endif |