summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--configure.ac7
-rw-r--r--man/radeon.man42
-rw-r--r--src/ati_pciids_gen.h22
-rw-r--r--src/atombios_crtc.c6
-rw-r--r--src/atombios_output.c53
-rw-r--r--src/legacy_crtc.c4
-rw-r--r--src/legacy_output.c69
-rw-r--r--src/pcidb/ati_pciids.csv22
-rw-r--r--src/radeon.h7
-rw-r--r--src/radeon_atombios.c12
-rw-r--r--src/radeon_chipinfo_gen.h22
-rw-r--r--src/radeon_chipset_gen.h22
-rw-r--r--src/radeon_commonfuncs.c5
-rw-r--r--src/radeon_crtc.c2
-rw-r--r--src/radeon_dri.c9
-rw-r--r--src/radeon_driver.c121
-rw-r--r--src/radeon_exa.c12
-rw-r--r--src/radeon_exa_funcs.c11
-rw-r--r--src/radeon_exa_render.c133
-rw-r--r--src/radeon_legacy_memory.c4
-rw-r--r--src/radeon_output.c31
-rw-r--r--src/radeon_pci_chipset_gen.h22
-rw-r--r--src/radeon_pci_device_match_gen.h22
-rw-r--r--src/radeon_probe.h6
-rw-r--r--src/radeon_reg.h29
-rw-r--r--src/radeon_textured_videofuncs.c20
26 files changed, 495 insertions, 220 deletions
diff --git a/configure.ac b/configure.ac
index 8a6000ae..28207d6f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.10.0.99,
+ 6.11.0.99,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
@@ -129,7 +129,7 @@ if test "x$EXA" = xyes; then
AC_MSG_RESULT(yes)
SAVE_CPPFLAGS="$CPPFLAGS"
- CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
+ CPPFLAGS="$CPPFLAGS $XORG_CFLAGS -DEXA_DRIVER_KNOWN_MAJOR=3"
AC_CHECK_HEADER(exa.h,
[have_exa_h="yes"], [have_exa_h="no"])
CPPFLAGS="$SAVE_CPPFLAGS"
@@ -138,7 +138,7 @@ else
fi
SAVE_CPPFLAGS="$CPPFLAGS"
-CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
+CPPFLAGS="$CPPFLAGS $XORG_CFLAGS -DEXA_DRIVER_KNOWN_MAJOR=3"
if test "x$have_exa_h" = xyes; then
AC_MSG_CHECKING([whether EXA version is at least 2.0.0])
AC_PREPROC_IFELSE([AC_LANG_PROGRAM([[
@@ -153,6 +153,7 @@ if test "x$have_exa_h" = xyes; then
if test "x$USE_EXA" = xyes; then
AC_DEFINE(USE_EXA, 1, [Build support for Exa])
+ AC_DEFINE(EXA_DRIVER_KNOWN_MAJOR, 3, [Major version of EXA we know how to handle])
fi
fi
diff --git a/man/radeon.man b/man/radeon.man
index 17b59a79..b9686b5a 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -34,8 +34,9 @@ option);
Full EXA 2D acceleration (not supported on R/RV6xx and R/RV/RS7xx);
.TP
\(bu
-Full XAA 2D acceleration (not supported on R/RV6xx and R/RV/RS7xx. XAA Render
-acceleration supported only on R/RV100, R/RV/RS2xx and RS3xx);
+Full XAA 2D acceleration (only on R/RV/RS1xx, R/RV/RS2xx, R/RV/RS3xx,
+R/RV/RS4xx, R/RV5xx, RS6xx. XAA Render acceleration supported only on R/RV100,
+R/RV/RS2xx and RS3xx);
.TP
\(bu
Textured XVideo acceleration (not supported on R/RV6xx and R/RV/RS7xx.
@@ -79,6 +80,9 @@ Radeon 8500, 9100, FireGL 8800/8700
.B RV250
Radeon 9000PRO/9000, M9
.TP 12
+.B RV280
+Radeon 9200PRO/9200/9200SE/9250, M9+
+.TP 12
.B RS300
Radeon 9100 IGP
.TP 12
@@ -88,9 +92,6 @@ Radeon 9200 IGP
.B RS400/RS480
Radeon XPRESS 200(M)/1100 IGP
.TP 12
-.B RV280
-Radeon 9200PRO/9200/9200SE/9250, M9+
-.TP 12
.B R300
Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1
.TP 12
@@ -145,12 +146,12 @@ Radeon HD 2900
.B RV610/RV630
Radeon HD 2400/2600
.TP 12
-.B RV670
-Radeon HD 3850/3870
-.TP 12
.B RV620/RV635
Radeon HD 3450/3470
.TP 12
+.B RV670
+Radeon HD 3850/3870
+.TP 12
.B RS780
Radeon HD 3100/3200/3300
.TP 12
@@ -257,7 +258,7 @@ PCI \-\- PCI bus
.br
AGP \-\- AGP bus
.br
-PCIE \-\- PCI Express (falls back to PCI at present)
+PCIE \-\- PCI Express bus
.br
(used only when DRI is enabled)
.br
@@ -449,7 +450,7 @@ The default is
.TP
.BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q
Enable load detection on the TV DAC. The TV DAC is used to drive both
-TV-OUT and analog monitors. Load detection is often unreliable in the
+TV-out and analog monitors. Load detection is often unreliable in the
TV DAC so it is disabled by default.
The default is
.B off.
@@ -537,7 +538,7 @@ The default value is
.B undefined.
.TP
.BI "Option \*qForceTVOut\*q \*q" boolean \*q
-Enable this option to force TV Out to always be detected as attached.
+Enable this option to force TV-out to always be detected as attached.
The default is
.B off
.TP
@@ -569,6 +570,25 @@ The default is
.SH SEE ALSO
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
+.IP " 1." 4
+Overview about radeon development code
+.RS 4
+\%http://cgit.freedesktop.org/xorg/driver/xf86-video-ati/
+.RE
+.IP " 2." 4
+Query the bugtracker for radeon bugs
+.RS 4
+.nf
+\%https://bugs.freedesktop.org/query.cgi?\:product=\:xorg&\:component=\:Driver/Radeon
+.fi
+.RE
+.IP " 3." 4
+Submit bugs & patches
+.RS 4
+.nf
+\%https://bugs.freedesktop.org/enter_bug.cgi?\:product=\:xorg&\:component=\:Driver/Radeon
+.fi
+.RE
.SH AUTHORS
.nf
Authors include:
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 6f23628a..d532f161 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -345,9 +345,15 @@
#define PCI_CHIP_RV770_9456 0x9456
#define PCI_CHIP_RV770_945A 0x945A
#define PCI_CHIP_RV770_945B 0x945B
+#define PCI_CHIP_RV770_946A 0x946A
+#define PCI_CHIP_RV770_946B 0x946B
+#define PCI_CHIP_RV770_947A 0x947A
+#define PCI_CHIP_RV770_947B 0x947B
#define PCI_CHIP_RV730_9487 0x9487
+#define PCI_CHIP_RV730_9489 0x9489
#define PCI_CHIP_RV730_948F 0x948F
#define PCI_CHIP_RV730_9490 0x9490
+#define PCI_CHIP_RV730_9491 0x9491
#define PCI_CHIP_RV730_9498 0x9498
#define PCI_CHIP_RV730_949C 0x949C
#define PCI_CHIP_RV730_949E 0x949E
@@ -363,19 +369,27 @@
#define PCI_CHIP_RV610_94C9 0x94C9
#define PCI_CHIP_RV610_94CB 0x94CB
#define PCI_CHIP_RV610_94CC 0x94CC
+#define PCI_CHIP_RV610_94CD 0x94CD
#define PCI_CHIP_RV670_9500 0x9500
#define PCI_CHIP_RV670_9501 0x9501
+#define PCI_CHIP_RV670_9504 0x9504
#define PCI_CHIP_RV670_9505 0x9505
+#define PCI_CHIP_RV670_9506 0x9506
#define PCI_CHIP_RV670_9507 0x9507
+#define PCI_CHIP_RV670_9508 0x9508
+#define PCI_CHIP_RV670_9509 0x9509
#define PCI_CHIP_RV670_950F 0x950F
#define PCI_CHIP_RV670_9511 0x9511
#define PCI_CHIP_RV670_9515 0x9515
+#define PCI_CHIP_RV670_9517 0x9517
+#define PCI_CHIP_RV670_9519 0x9519
#define PCI_CHIP_RV710_9540 0x9540
#define PCI_CHIP_RV710_9541 0x9541
#define PCI_CHIP_RV710_954E 0x954E
#define PCI_CHIP_RV710_954F 0x954F
#define PCI_CHIP_RV710_9552 0x9552
#define PCI_CHIP_RV710_9553 0x9553
+#define PCI_CHIP_RV710_9555 0x9555
#define PCI_CHIP_RV630_9580 0x9580
#define PCI_CHIP_RV630_9581 0x9581
#define PCI_CHIP_RV630_9583 0x9583
@@ -388,12 +402,16 @@
#define PCI_CHIP_RV630_958C 0x958C
#define PCI_CHIP_RV630_958D 0x958D
#define PCI_CHIP_RV630_958E 0x958E
-#define PCI_CHIP_RV710_9592 0x9592
+#define PCI_CHIP_RV630_958F 0x958F
+#define PCI_CHIP_RV710_9542 0x9542
#define PCI_CHIP_RV620_95C0 0x95C0
#define PCI_CHIP_RV620_95C2 0x95C2
#define PCI_CHIP_RV620_95C4 0x95C4
#define PCI_CHIP_RV620_95C5 0x95C5
+#define PCI_CHIP_RV620_95C6 0x95C6
#define PCI_CHIP_RV620_95C7 0x95C7
+#define PCI_CHIP_RV620_95C9 0x95C9
+#define PCI_CHIP_RV620_95CC 0x95CC
#define PCI_CHIP_RV620_95CD 0x95CD
#define PCI_CHIP_RV620_95CE 0x95CE
#define PCI_CHIP_RV620_95CF 0x95CF
@@ -404,6 +422,8 @@
#define PCI_CHIP_RV635_9599 0x9599
#define PCI_CHIP_RV635_9591 0x9591
#define PCI_CHIP_RV635_9593 0x9593
+#define PCI_CHIP_RV635_9595 0x9595
+#define PCI_CHIP_RV635_959B 0x959B
#define PCI_CHIP_RS780_9610 0x9610
#define PCI_CHIP_RS780_9611 0x9611
#define PCI_CHIP_RS780_9612 0x9612
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 32997407..5c26ef82 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -465,8 +465,8 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
@@ -491,6 +491,8 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
if (info->DispPriority)
RADEONInitDispBandwidth(pScrn);
+ radeon_crtc->initialized = TRUE;
+
if (tilingChanged) {
/* need to redraw front buffer, I guess this can be considered a hack ? */
/* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 0827d746..c4baa130 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -70,7 +70,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
unsigned char *space;
- int index, num = 0;
+ int index = 0, num = 0;
if (radeon_encoder == NULL)
return ATOM_NOT_IMPLEMENTED;
@@ -264,7 +264,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 disp_data2;
AtomBiosArgRec data;
unsigned char *space;
- int index;
+ int index = 0;
int major, minor;
int lvds_misc = 0;
@@ -458,7 +458,7 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode)
DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data;
AtomBiosArgRec data;
unsigned char *space;
- int index, major, minor, num = 0;
+ int index = 0, major, minor, num = 0;
if (radeon_encoder == NULL)
return ATOM_NOT_IMPLEMENTED;
@@ -562,7 +562,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
union dig_transmitter_control disp_data;
AtomBiosArgRec data;
unsigned char *space;
- int index, num = 0;
+ int index = 0, num = 0;
int major, minor;
if (radeon_encoder == NULL)
@@ -1194,6 +1194,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
switch (mode) {
case DPMSModeOn:
+ radeon_encoder->devices |= radeon_output->active_device;
if (is_dig)
(void)atombios_dig_dpms(output, mode);
else {
@@ -1209,12 +1210,12 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
ErrorF("Output %s enable failed\n",
device_name[radeon_get_device_index(radeon_output->active_device)]);
}
- radeon_encoder->use_count++;
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- if (radeon_encoder->use_count < 2) {
+ radeon_encoder->devices &= ~(radeon_output->active_device);
+ if (!radeon_encoder->devices) {
if (is_dig)
(void)atombios_dig_dpms(output, mode);
else {
@@ -1232,8 +1233,6 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
device_name[radeon_get_device_index(radeon_output->active_device)]);
}
}
- if (radeon_encoder->use_count > 0)
- radeon_encoder->use_count--;
break;
}
}
@@ -1268,7 +1267,43 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
case 1:
default:
crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
- crtc_src_param.ucDevice = radeon_get_device_index(radeon_output->active_device);
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT)
+ crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX;
+ else
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+ case ENCODER_OBJECT_ID_INTERNAL_DDI:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+ crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT))
+ crtc_src_param.ucDevice = ATOM_DEVICE_TV1_INDEX;
+ else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT))
+ crtc_src_param.ucDevice = ATOM_DEVICE_CV_INDEX;
+ else
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT))
+ crtc_src_param.ucDevice = ATOM_DEVICE_TV1_INDEX;
+ else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT))
+ crtc_src_param.ucDevice = ATOM_DEVICE_CV_INDEX;
+ else
+ crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX;
+ break;
+ }
data.exec.pspace = &crtc_src_param;
/*ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);*/
break;
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index cba1b5f3..b8c53806 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -1832,7 +1832,9 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
radeon_update_tv_routing(pScrn, info->ModeReg);
if (info->DispPriority)
- RADEONInitDispBandwidth(pScrn);
+ RADEONInitDispBandwidth(pScrn);
+
+ radeon_crtc->initialized = TRUE;
if (tilingChanged) {
/* need to redraw front buffer, I guess this can be considered a hack ? */
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 82291e57..62235311 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -903,6 +903,7 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
+ radeon_encoder->devices |= radeon_output->active_device;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
{
@@ -984,35 +985,35 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
RADEONDacPowerSet(pScrn, TRUE, FALSE);
break;
}
- radeon_encoder->use_count++;
break;
case DPMSModeOff:
case DPMSModeSuspend:
case DPMSModeStandby:
- switch (radeon_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_LVDS:
- if (radeon_encoder->use_count < 2) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- ErrorF("disable LVDS\n");
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ radeon_encoder->devices &= ~(radeon_output->active_device);
+ if (!radeon_encoder->devices) {
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ ErrorF("disable LVDS\n");
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
}
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
ErrorF("disable FP1\n");
tmp = INREG(RADEON_FP_GEN_CNTL);
tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
@@ -1026,10 +1027,8 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON |
RS400_TMDS_2ND_EN);
}
- }
break;
- case ENCODER_OBJECT_ID_INTERNAL_DVO1:
- if (radeon_encoder->use_count < 2) {
+ case ENCODER_OBJECT_ID_INTERNAL_DVO1:
ErrorF("disable FP2\n");
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= RADEON_FP2_BLANK_EN;
@@ -1046,20 +1045,16 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN;
}
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC1:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
ErrorF("disable primary dac\n");
tmp = INREG(RADEON_CRTC_EXT_CNTL);
tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
RADEONDacPowerSet(pScrn, FALSE, TRUE);
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
ErrorF("disable TV\n");
tmp = INREG(RADEON_TV_MASTER_CNTL);
@@ -1081,11 +1076,9 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
}
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
+ break;
}
- break;
}
- if (radeon_encoder->use_count > 0)
- radeon_encoder->use_count--;
break;
}
}
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index aea09311..4d4e6256 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -346,9 +346,15 @@
"0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)"
"0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870"
"0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98"
+"0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750"
+"0x946B","RV770_946B","RV770",1,,,,,"ATI M98"
+"0x947A","RV770_947A","RV770",1,,,,,"ATI M98"
+"0x947B","RV770_947B","RV770",1,,,,,"ATI M98"
"0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)"
+"0x9489","RV730_9489","RV730",1,,,,,"ATI FirePro M5750"
"0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)"
"0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]"
+"0x9491","RV730_9491","RV730",,,,,,"ATI RADEON E4600"
"0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]"
"0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)"
"0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)"
@@ -364,19 +370,27 @@
"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400"
"0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400"
"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610"
+"0x94CD","RV610_94CD","RV610",,,,,,"ATI FireMV 2260"
"0x9500","RV670_9500","RV670",,,,,,"ATI RV670"
"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870"
+"0x9504","RV670_9504","RV670",1,,,,,"ATI Mobility Radeon HD 3850"
"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850"
+"0x9506","RV670_9506","RV670",1,,,,,"ATI Mobility Radeon HD 3850 X2"
"0x9507","RV670_9507","RV670",,,,,,"ATI RV670"
+"0x9508","RV670_9508","RV670",1,,,,,"ATI Mobility Radeon HD 3870"
+"0x9509","RV670_9509","RV670",1,,,,,"ATI Mobility Radeon HD 3870 X2"
"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2"
"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700"
"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850"
+"0x9517","RV670_9517","RV670",,,,,,"ATI Radeon HD3690"
+"0x9519","RV670_9519","RV670",,,,,,"AMD Firestream 9170"
"0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550"
"0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710"
"0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710"
"0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350"
"0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series"
"0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
+"0x9555","RV710_9555","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
@@ -389,12 +403,16 @@
"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
"0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE"
-"0x9592","RV710_9592","RV710",,,,,,"ATI Radeon RV710"
+"0x958F","RV630_958F","RV630",1,,,,,"ATI Mobility FireGL Graphics Processor"
+"0x9542","RV710_9542","RV710",,,,,,"ATI Radeon RV710"
"0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470"
"0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430"
"0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series"
"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450"
+"0x95C6","RV620_95C6","RV620",,,,,,"ATI Radeon HD 3450"
"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430"
+"0x95C9","RV620_95C9","RV620",,,,,,"ATI Radeon HD 3450"
+"0x95CC","RV620_95CC","RV620",,,,,,"ATI FirePro V3700"
"0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450"
"0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260"
"0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260"
@@ -405,6 +423,8 @@
"0x9599","RV635_9599","RV635",,,,,,"ATI Radeon HD 3600 PRO"
"0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650"
"0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670"
+"0x9595","RV635_9595","RV635",1,,,,,"ATI Mobility FireGL V5700"
+"0x959B","RV635_959B","RV635",1,,,,,"ATI Mobility FireGL V5725"
"0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
"0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
diff --git a/src/radeon.h b/src/radeon.h
index 2edad514..a7ed95e4 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -915,6 +915,9 @@ typedef struct {
/* some server chips have a hardcoded edid in the bios so that they work with KVMs */
Bool get_hardcoded_edid_from_bios;
+ int virtualX;
+ int virtualY;
+
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
@@ -1023,11 +1026,11 @@ extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
#ifdef XF86DRI
extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop, int enable);
+ int crtc, int start, int stop);
#endif
extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop, int enable);
+ int crtc, int start, int stop);
/* radeon_crtc.c */
extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 61eb62b0..34bf1dc1 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1570,6 +1570,16 @@ static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
(info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
info->BiosConnector[index].devices &= ~(ATOM_DEVICE_CRT_SUPPORT);
}
+
+ /* ASUS HD 3600 XT board lists the DVI port as HDMI */
+ if ((info->Chipset == PCI_CHIP_RV635_9598) &&
+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) &&
+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01da)) {
+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_B)
+ info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D;
+ }
+
+
}
uint32_t
@@ -1644,7 +1654,7 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
info->encoders[device_index] = (radeon_encoder_ptr)xcalloc(1,sizeof(radeon_encoder_rec));
if (info->encoders[device_index] != NULL) {
info->encoders[device_index]->encoder_id = encoder_id;
- info->encoders[device_index]->use_count = 0;
+ info->encoders[device_index]->devices = 0;
info->encoders[device_index]->dev_priv = NULL;
// add dev_priv stuff
switch (encoder_id) {
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 627520b4..eb2df17b 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -265,9 +265,15 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
{ 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x947B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
{ 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
+ { 0x9489, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
{ 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
+ { 0x9491, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
@@ -283,19 +289,27 @@ RADEONCardInfo RADEONCards[] = {
{ 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94CD, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9504, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9506, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9508, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
+ { 0x9509, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9517, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9519, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
{ 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
+ { 0x9555, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
{ 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
@@ -308,12 +322,16 @@ RADEONCardInfo RADEONCards[] = {
{ 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9592, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
+ { 0x958F, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
+ { 0x9542, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95C6, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95C9, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95CC, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
@@ -324,6 +342,8 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
+ { 0x9595, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
+ { 0x959B, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index b8a8a650..3c86ae6b 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -265,9 +265,15 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" },
{ PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" },
{ PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" },
+ { PCI_CHIP_RV770_946A, "ATI FirePro M7750" },
+ { PCI_CHIP_RV770_946B, "ATI M98" },
+ { PCI_CHIP_RV770_947A, "ATI M98" },
+ { PCI_CHIP_RV770_947B, "ATI M98" },
{ PCI_CHIP_RV730_9487, "ATI Radeon RV730 (AGP)" },
+ { PCI_CHIP_RV730_9489, "ATI FirePro M5750" },
{ PCI_CHIP_RV730_948F, "ATI Radeon RV730 (AGP)" },
{ PCI_CHIP_RV730_9490, "ATI RV730XT [Radeon HD 4670]" },
+ { PCI_CHIP_RV730_9491, "ATI RADEON E4600" },
{ PCI_CHIP_RV730_9498, "ATI RV730 PRO [Radeon HD 4650]" },
{ PCI_CHIP_RV730_949C, "ATI FirePro V7750 (FireGL)" },
{ PCI_CHIP_RV730_949E, "ATI FirePro V5700 (FireGL)" },
@@ -283,19 +289,27 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" },
{ PCI_CHIP_RV610_94CB, "ATI RADEON E2400" },
{ PCI_CHIP_RV610_94CC, "ATI RV610" },
+ { PCI_CHIP_RV610_94CD, "ATI FireMV 2260" },
{ PCI_CHIP_RV670_9500, "ATI RV670" },
{ PCI_CHIP_RV670_9501, "ATI Radeon HD3870" },
+ { PCI_CHIP_RV670_9504, "ATI Mobility Radeon HD 3850" },
{ PCI_CHIP_RV670_9505, "ATI Radeon HD3850" },
+ { PCI_CHIP_RV670_9506, "ATI Mobility Radeon HD 3850 X2" },
{ PCI_CHIP_RV670_9507, "ATI RV670" },
+ { PCI_CHIP_RV670_9508, "ATI Mobility Radeon HD 3870" },
+ { PCI_CHIP_RV670_9509, "ATI Mobility Radeon HD 3870 X2" },
{ PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" },
{ PCI_CHIP_RV670_9511, "ATI FireGL V7700" },
{ PCI_CHIP_RV670_9515, "ATI Radeon HD3850" },
+ { PCI_CHIP_RV670_9517, "ATI Radeon HD3690" },
+ { PCI_CHIP_RV670_9519, "AMD Firestream 9170" },
{ PCI_CHIP_RV710_9540, "ATI Radeon HD 4550" },
{ PCI_CHIP_RV710_9541, "ATI Radeon RV710" },
{ PCI_CHIP_RV710_954E, "ATI Radeon RV710" },
{ PCI_CHIP_RV710_954F, "ATI Radeon HD 4350" },
{ PCI_CHIP_RV710_9552, "ATI Mobility Radeon 4300 Series" },
{ PCI_CHIP_RV710_9553, "ATI Mobility Radeon 4500 Series" },
+ { PCI_CHIP_RV710_9555, "ATI Mobility Radeon 4500 Series" },
{ PCI_CHIP_RV630_9580, "ATI RV630" },
{ PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
{ PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
@@ -308,12 +322,16 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
{ PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
{ PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" },
- { PCI_CHIP_RV710_9592, "ATI Radeon RV710" },
+ { PCI_CHIP_RV630_958F, "ATI Mobility FireGL Graphics Processor" },
+ { PCI_CHIP_RV710_9542, "ATI Radeon RV710" },
{ PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" },
{ PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" },
{ PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" },
{ PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" },
+ { PCI_CHIP_RV620_95C6, "ATI Radeon HD 3450" },
{ PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" },
+ { PCI_CHIP_RV620_95C9, "ATI Radeon HD 3450" },
+ { PCI_CHIP_RV620_95CC, "ATI FirePro V3700" },
{ PCI_CHIP_RV620_95CD, "ATI FireMV 2450" },
{ PCI_CHIP_RV620_95CE, "ATI FireMV 2260" },
{ PCI_CHIP_RV620_95CF, "ATI FireMV 2260" },
@@ -324,6 +342,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV635_9599, "ATI Radeon HD 3600 PRO" },
{ PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" },
{ PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" },
+ { PCI_CHIP_RV635_9595, "ATI Mobility FireGL V5700" },
+ { PCI_CHIP_RV635_959B, "ATI Mobility FireGL V5725" },
{ PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" },
{ PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" },
{ PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" },
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index f7a1a602..eabd87df 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -628,16 +628,13 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
/* inserts a wait for vline in the command stream */
void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop, Bool enable)
+ int crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
uint32_t offset;
ACCEL_PREAMBLE();
- if (!enable)
- return;
-
if ((crtc < 0) || (crtc > 1))
return;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index ec6a6626..60140d6b 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -608,6 +608,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
pRADEONEnt->Controller[0]->crtc_id = 0;
pRADEONEnt->Controller[0]->crtc_offset = 0;
+ pRADEONEnt->Controller[0]->initialized = FALSE;
if (info->allowColorTiling)
pRADEONEnt->Controller[0]->can_tile = 1;
else
@@ -632,6 +633,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+ pRADEONEnt->Controller[1]->initialized = FALSE;
if (info->allowColorTiling)
pRADEONEnt->Controller[1]->can_tile = 1;
else
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index ba5fbcee..45c927f2 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -737,6 +737,8 @@ typedef struct {
/* Keep sorted by hostbridge vendor and device */
static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
+ /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */
+ { PCI_VENDOR_INTEL,0x2550, PCI_VENDOR_ATI,0x4152, 0x1458,0x4038, 4 },
/* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */
{ PCI_VENDOR_INTEL,0x2570, PCI_VENDOR_ATI,0x4a4e, PCI_VENDOR_DELL,0x5106, 4 },
/* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */
@@ -769,8 +771,12 @@ static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
{ 0x1106,0x3189, PCI_VENDOR_ATI,0x5964, 0x148c,0x2073, 4 },
/* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */
{ 0x1106,0x0691, PCI_VENDOR_ATI,0x5960, 0x1043,0x0054, 2 },
+ /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */
+ { 0x1106,0x0691, PCI_VENDOR_ATI,0x5960, 0x1043,0x004c, 2 },
/* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */
{ 0x1106,0x0204, PCI_VENDOR_ATI,0x5960, 0x17af,0x2020, 4 },
+ /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */
+ { 0x1106,0x0269, PCI_VENDOR_ATI,0x4153, 0x1043,0x003c, 4 },
/* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */
{ 0x1002,0xcbb2, PCI_VENDOR_ATI,0x5c61, 0x104d,0x8175, 1 },
@@ -2306,11 +2312,10 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- int page_size = getpagesize();
int ret_size;
int num_pages;
- num_pages = (info->dri->pciAperSize * 1024 * 1024) / page_size;
+ num_pages = (info->dri->pciAperSize * 1024 * 1024) / 4096;
ret_size = num_pages * sizeof(unsigned int);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 75feca49..1171de48 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -578,7 +578,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
data = INREG(RS690_MC_DATA);
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
- OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
+ OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
data = INREG(RS600_MC_DATA);
} else if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
@@ -591,7 +591,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
(void)INREG(R300_MC_IND_INDEX);
data = INREG(R300_MC_IND_DATA);
-
+
OUTREG(R300_MC_IND_INDEX, 0);
(void)INREG(R300_MC_IND_INDEX);
}
@@ -612,10 +612,10 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data)
OUTREG(RS690_MC_DATA, data);
OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
- OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) |
- RS600_MC_INDEX_WR_EN));
+ OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
+ RS600_MC_IND_CITF_ARB0 |
+ RS600_MC_IND_WR_EN));
OUTREG(RS600_MC_DATA, data);
- OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK);
} else if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
(void)INREG(AVIVO_MC_INDEX);
@@ -635,17 +635,20 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data)
static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- /* no idea where this is on r600 yet */
- return TRUE;
+ if (INREG(R600_SRBM_STATUS) & 0x3f00)
+ return FALSE;
+ else
+ return TRUE;
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
return TRUE;
else
return FALSE;
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
- if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
+ if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE)
return TRUE;
else
return FALSE;
@@ -693,8 +696,8 @@ static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
if (mask & LOC_FB)
OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc);
- /* if (mask & LOC_AGP)
- OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/
+ if (mask & LOC_AGP)
+ OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);
} else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
if (mask & LOC_FB)
@@ -745,7 +748,7 @@ static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t
if (mask & LOC_FB)
*fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION);
if (mask & LOC_AGP) {
- *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
+ *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
@@ -1258,8 +1261,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- uint32_t mem_size;
- uint32_t aper_size;
+ uint64_t mem_size;
+ uint64_t aper_size;
radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location,
&info->mc_agp_location, &info->mc_agp_location_hi);
@@ -1306,7 +1309,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
else
#endif
{
- uint32_t aper0_base;
+ uint64_t aper0_base;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
aper0_base = INREG(R600_CONFIG_F0_BASE);
@@ -1330,33 +1333,29 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
aper0_base &= ~(mem_size - 1);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->mc_fb_location = (aper0_base >> 24) |
- (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
+ uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) |
+ (((aper0_base + mem_size - 1) >> 8) & 0xffff0000);
+ info->mc_fb_location = mc_fb & 0xffffffff;
ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
} else {
- info->mc_fb_location = (aper0_base >> 16) |
+ uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) |
((aper0_base + mem_size - 1) & 0xffff0000U);
+ info->mc_fb_location = mc_fb & 0xffffffff;
}
}
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
} else {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
+ info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
}
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
*/
-
- if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
- } else {
- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
- }
- info->mc_agp_location = 0x003f0000;
- } else
- info->mc_agp_location = 0xffffffc0;
+ if (IS_AVIVO_VARIANT)
+ info->mc_agp_location = 0x003f0000;
+ else
+ info->mc_agp_location = 0xffffffc0;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONInitMemoryMap() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -1503,6 +1502,9 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
info->dri->newMemoryMap = TRUE;
#endif /* XF86DRI */
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ return aper_size;
+
/* Set HDP_APER_CNTL only on cards that are known not to be broken,
* that is has the 2nd generation multifunction PCI interface
*/
@@ -1511,7 +1513,7 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
info->ChipFamily == CHIP_FAMILY_RV380 ||
info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410 ||
- IS_AVIVO_VARIANT) {
+ IS_AVIVO_VARIANT) {
OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
~RADEON_HDP_APER_CNTL);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -1588,9 +1590,10 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
if (pScrn->videoRam > accessible)
pScrn->videoRam = accessible;
- if (!IS_AVIVO_VARIANT)
+ if (!IS_AVIVO_VARIANT) {
info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
- info->BusCntl = INREG(RADEON_BUS_CNTL);
+ info->BusCntl = INREG(RADEON_BUS_CNTL);
+ }
RADEONGetVRamType(pScrn);
@@ -1881,6 +1884,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP)
info->cardType = CARD_PCIE;
+ /* not sure about gart table requirements */
+ if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP)
+ info->cardType = CARD_PCIE;
+
if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) {
if (strcmp(s, "AGP") == 0) {
info->cardType = CARD_AGP;
@@ -2151,11 +2158,10 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
if (info->Chipset == PCI_CHIP_RN50_515E ||
info->Chipset == PCI_CHIP_RN50_5969 ||
- info->ChipFamily == CHIP_FAMILY_RS600 ||
info->ChipFamily >= CHIP_FAMILY_R600) {
if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering for RN50/RS600/R600 forced on -- "
+ "Direct rendering for RN50/R600 forced on -- "
"This is NOT officially supported at the hardware level "
"and may cause instability or lockups\n");
} else {
@@ -3256,6 +3262,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->crtc_on = FALSE;
info->crtc2_on = FALSE;
+ /* save the real front buffer size
+ * it changes with randr, rotation, etc.
+ */
+ info->virtualX = pScrn->virtualX;
+ info->virtualY = pScrn->virtualY;
+
RADEONSave(pScrn);
/* set initial bios scratch reg state */
@@ -5047,8 +5059,10 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
"RADEONRestore\n");
#if X_BYTE_ORDER == X_BIG_ENDIAN
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
+ if (info->ChipFamily < CHIP_FAMILY_R600) {
+ RADEONWaitForFifo(pScrn, 1);
+ OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
+ }
#endif
RADEONBlank(pScrn);
@@ -5517,8 +5531,17 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
if (info->cardType == CARD_PCIE &&
info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);
+
/* we need to backup the PCIE GART TABLE from fb memory */
+ OUTREG(RADEON_SURFACE_CNTL, 0);
+#endif
memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ OUTREG(RADEON_SURFACE_CNTL, sctrl);
+#endif
}
/* get the DRI back into shape after resume */
@@ -5571,8 +5594,17 @@ void RADEONLeaveVT(int scrnIndex, int flags)
if (info->cardType == CARD_PCIE &&
info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);
+
/* we need to backup the PCIE GART TABLE from fb memory */
+ OUTREG(RADEON_SURFACE_CNTL, 0);
+#endif
memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ OUTREG(RADEON_SURFACE_CNTL, sctrl);
+#endif
}
/* Make sure 3D clients will re-upload textures to video RAM */
@@ -5592,18 +5624,24 @@ void RADEONLeaveVT(int scrnIndex, int flags)
}
#endif
-#ifndef HAVE_FREE_SHADOW
+
for (i = 0; i < config->num_crtc; i++) {
xf86CrtcPtr crtc = config->crtc[i];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->initialized = FALSE;
+#ifndef HAVE_FREE_SHADOW
if (crtc->rotatedPixmap || crtc->rotatedData) {
crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap,
crtc->rotatedData);
crtc->rotatedPixmap = NULL;
crtc->rotatedData = NULL;
}
+#endif
}
-#else
+
+#ifdef HAVE_FREE_SHADOW
xf86RotateFreeShadow(pScrn);
#endif
@@ -5626,6 +5664,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONCloseScreen\n");
@@ -5635,6 +5675,13 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
*/
info->accelOn = FALSE;
+ for (i = 0; i < config->num_crtc; i++) {
+ xf86CrtcPtr crtc = config->crtc[i];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->initialized = FALSE;
+ }
+
#ifdef XF86DRI
#ifdef DAMAGE
if (info->dri && info->dri->pDamage) {
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 5e236458..ae681462 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -222,7 +222,7 @@ int RADEONBiggerCrtcArea(PixmapPtr pPix)
#if X_BYTE_ORDER == X_BIG_ENDIAN
-static unsigned long swapper_surfaces[3];
+static unsigned long swapper_surfaces[6];
static Bool RADEONPrepareAccess(PixmapPtr pPix, int index)
{
@@ -521,10 +521,16 @@ extern void ExaOffscreenMarkUsed(PixmapPtr);
unsigned long long
RADEONTexOffsetStart(PixmapPtr pPix)
{
+ RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+ unsigned long long offset;
exaMoveInPixmap(pPix);
ExaOffscreenMarkUsed(pPix);
- return RADEONPTR(xf86Screens[pPix->drawable.pScreen->myNum])->fbLocation +
- exaGetPixmapOffset(pPix);
+ offset = exaGetPixmapOffset(pPix);
+
+ if (offset > info->FbMapSize)
+ return ~0ULL;
+ else
+ return info->fbLocation + offset;
}
#endif
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index cd97cc6e..dec02856 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -56,8 +56,6 @@
#include "radeon.h"
-#include "exa.h"
-
static int
FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
{
@@ -129,7 +127,8 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
TRACE;
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix, RADEONBiggerCrtcArea(pPix), y1, y2, info->accel_state->vsync);
+ if (info->accel_state->vsync)
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix, RADEONBiggerCrtcArea(pPix), y1, y2);
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_DST_Y_X, (y1 << 16) | x1);
@@ -230,7 +229,8 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
dstY += h - 1;
}
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h, info->accel_state->vsync);
+ if (info->accel_state->vsync)
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h);
BEGIN_ACCEL(3);
@@ -281,7 +281,8 @@ RADEONUploadToScreenCP(PixmapPtr pDst, int x, int y, int w, int h,
RADEON_SWITCH_TO_2D();
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), y, y + h, info->accel_state->vsync);
+ if (info->accel_state->vsync)
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), y, y + h);
while ((buf = RADEONHostDataBlit(pScrn,
cpp, w, dst_pitch_off, &buf_pitch,
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 0c84384f..571204af 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -284,7 +284,7 @@ static Bool RADEONSetupSourceTile(PicturePtr pPict,
info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = FALSE;
info->accel_state->src_tile_width = info->accel_state->src_tile_height = 65536; /* "infinite" */
- if (pPict->repeatType == RepeatNormal) {
+ if (pPict->repeat && pPict->repeatType != RepeatPad) {
Bool badPitch = needMatchingPitch && !RADEONPitchMatches(pPix);
int w = pPict->pDrawable->width;
@@ -297,7 +297,12 @@ static Bool RADEONSetupSourceTile(PicturePtr pPict,
} else {
info->accel_state->need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
info->accel_state->need_src_tile_y = (h & (h - 1)) != 0;
-
+
+ if ((info->accel_state->need_src_tile_x ||
+ info->accel_state->need_src_tile_y) &&
+ pPict->repeatType != RepeatNormal)
+ RADEON_FALLBACK(("Can only tile RepeatNormal at this time\n"));
+
if (!canTile1d)
info->accel_state->need_src_tile_x =
info->accel_state->need_src_tile_y =
@@ -369,7 +374,7 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
+
for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++)
{
if (R100TexFormats[i].fmt == pPict->format)
@@ -404,19 +409,21 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
- switch (pPict->repeatType) {
- case RepeatNormal:
- txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP;
- break;
- case RepeatPad:
- txfilter |= RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST;
- break;
- case RepeatReflect:
- txfilter |= RADEON_CLAMP_S_MIRROR | RADEON_CLAMP_T_MIRROR;
- break;
- case RepeatNone:
- /* Nothing to do */
- break;
+ if (repeat) {
+ switch (pPict->repeatType) {
+ case RepeatNormal:
+ txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP;
+ break;
+ case RepeatPad:
+ txfilter |= RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST;
+ break;
+ case RepeatReflect:
+ txfilter |= RADEON_CLAMP_S_MIRROR | RADEON_CLAMP_T_MIRROR;
+ break;
+ case RepeatNone:
+ /* Nothing to do */
+ break;
+ }
}
BEGIN_ACCEL(5);
@@ -740,19 +747,21 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
- switch (pPict->repeatType) {
- case RepeatNormal:
- txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP;
- break;
- case RepeatPad:
- txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST;
- break;
- case RepeatReflect:
- txfilter |= R200_CLAMP_S_MIRROR | R200_CLAMP_T_MIRROR;
- break;
- case RepeatNone:
- /* Nothing to do */
- break;
+ if (repeat) {
+ switch (pPict->repeatType) {
+ case RepeatNormal:
+ txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP;
+ break;
+ case RepeatPad:
+ txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST;
+ break;
+ case RepeatReflect:
+ txfilter |= R200_CLAMP_S_MIRROR | R200_CLAMP_T_MIRROR;
+ break;
+ case RepeatNone:
+ /* Nothing to do */
+ break;
+ }
}
BEGIN_ACCEL(6);
@@ -1088,32 +1097,36 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txfilter = (unit << R300_TX_ID_SHIFT);
- switch (pPict->repeatType) {
- case RepeatNormal:
- if (unit != 0 || !info->accel_state->need_src_tile_x)
- txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
- else
- txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
+ if (pPict->repeat) {
+ switch (pPict->repeatType) {
+ case RepeatNormal:
+ if (unit != 0 || !info->accel_state->need_src_tile_x)
+ txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
+ else
+ txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
- if (unit != 0 || !info->accel_state->need_src_tile_y)
- txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
- else
- txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
+ if (unit != 0 || !info->accel_state->need_src_tile_y)
+ txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
+ else
+ txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
- break;
- case RepeatPad:
- txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST);
- break;
- case RepeatReflect:
- txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_MIRROR) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_MIRROR);
- break;
- case RepeatNone:
+ break;
+ case RepeatPad:
+ txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST);
+ break;
+ case RepeatReflect:
+ txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_MIRROR) |
+ R300_TX_CLAMP_T(R300_TX_CLAMP_MIRROR);
+ break;
+ case RepeatNone:
+ txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL) |
+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
+ break;
+ }
+ } else
txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
- break;
- }
+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
switch (pPict->filter) {
case PictFilterNearest:
@@ -2002,13 +2015,14 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
}
#endif
-static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
+static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
+ RADEONInfoPtr info,
+ PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
int dstX, int dstY,
int w, int h)
{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
int vtx_count;
xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
static xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
@@ -2056,7 +2070,8 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
} else
vtx_count = 4;
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h, info->accel_state->vsync);
+ if (info->accel_state->vsync)
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h);
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
@@ -2167,7 +2182,9 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
- FUNC_NAME(RadeonCompositeTile)(pDst,
+ FUNC_NAME(RadeonCompositeTile)(pScrn,
+ info,
+ pDst,
srcX, srcY,
maskX, maskY,
dstX, dstY,
@@ -2201,7 +2218,9 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
w = remainingWidth;
remainingWidth -= w;
- FUNC_NAME(RadeonCompositeTile)(pDst,
+ FUNC_NAME(RadeonCompositeTile)(pScrn,
+ info,
+ pDst,
tileSrcX, tileSrcY,
tileMaskX, tileMaskY,
tileDstX, tileDstY,
diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c
index 2a9ee940..861fd979 100644
--- a/src/radeon_legacy_memory.c
+++ b/src/radeon_legacy_memory.c
@@ -93,10 +93,10 @@ void
radeon_legacy_free_memory(ScrnInfoPtr pScrn,
void *mem_struct)
{
- ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
-
#ifdef USE_EXA
+ ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
+
if (info->useEXA) {
ExaOffscreenArea *area = mem_struct;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index ba4cb7f1..897c6a21 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -510,10 +510,12 @@ radeon_mode_prepare(xf86OutputPtr output)
xf86CrtcPtr other_crtc = loop_output->crtc;
RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
if (other_crtc->enabled) {
- radeon_crtc_dpms(other_crtc, DPMSModeOff);
- if (IS_AVIVO_VARIANT)
- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1);
- radeon_dpms(loop_output, DPMSModeOff);
+ if (other_radeon_crtc->initialized) {
+ radeon_crtc_dpms(other_crtc, DPMSModeOff);
+ if (IS_AVIVO_VARIANT)
+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1);
+ radeon_dpms(loop_output, DPMSModeOff);
+ }
}
}
}
@@ -553,10 +555,12 @@ radeon_mode_commit(xf86OutputPtr output)
xf86CrtcPtr other_crtc = loop_output->crtc;
RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
if (other_crtc->enabled) {
- radeon_crtc_dpms(other_crtc, DPMSModeOn);
- if (IS_AVIVO_VARIANT)
- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0);
- radeon_dpms(loop_output, DPMSModeOn);
+ if (other_radeon_crtc->initialized) {
+ radeon_crtc_dpms(other_crtc, DPMSModeOn);
+ if (IS_AVIVO_VARIANT)
+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0);
+ radeon_dpms(loop_output, DPMSModeOn);
+ }
}
}
}
@@ -1143,7 +1147,7 @@ radeon_create_resources(xf86OutputPtr output)
}
#endif
- if (radeon_output->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
+ if (radeon_output->devices & (ATOM_DEVICE_CRT_SUPPORT | ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
load_detection_atom = MAKE_ATOM("load_detection");
range[0] = 0; /* off */
@@ -1844,7 +1848,10 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- radeon_output->rmx_type = RMX_OFF;
+ if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT))
+ radeon_output->rmx_type = RMX_FULL;
+ else
+ radeon_output->rmx_type = RMX_OFF;
if (!IS_AVIVO_VARIANT) {
if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) {
@@ -2465,14 +2472,10 @@ static int
radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn);
int o;
int index_mask = 0;
- if (IS_DCE3_VARIANT)
- return index_mask;
-
/* LVDS is too wacky */
if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT))
return index_mask;
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 525eafaf..31b032a9 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -265,9 +265,15 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA },
{ PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA },
{ PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_947B, PCI_CHIP_RV770_947B, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA },
+ { PCI_CHIP_RV730_9489, PCI_CHIP_RV730_9489, RES_SHARED_VGA },
{ PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA },
+ { PCI_CHIP_RV730_9491, PCI_CHIP_RV730_9491, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA },
{ PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA },
{ PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA },
@@ -283,19 +289,27 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94CD, PCI_CHIP_RV610_94CD, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9504, PCI_CHIP_RV670_9504, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9506, PCI_CHIP_RV670_9506, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9508, PCI_CHIP_RV670_9508, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9509, PCI_CHIP_RV670_9509, RES_SHARED_VGA },
{ PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9517, PCI_CHIP_RV670_9517, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9519, PCI_CHIP_RV670_9519, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA },
{ PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA },
{ PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA },
+ { PCI_CHIP_RV710_9555, PCI_CHIP_RV710_9555, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
@@ -308,12 +322,16 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
- { PCI_CHIP_RV710_9592, PCI_CHIP_RV710_9592, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958F, PCI_CHIP_RV630_958F, RES_SHARED_VGA },
+ { PCI_CHIP_RV710_9542, PCI_CHIP_RV710_9542, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95C6, PCI_CHIP_RV620_95C6, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95C9, PCI_CHIP_RV620_95C9, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95CC, PCI_CHIP_RV620_95CC, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA },
@@ -324,6 +342,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV635_9599, PCI_CHIP_RV635_9599, RES_SHARED_VGA },
{ PCI_CHIP_RV635_9591, PCI_CHIP_RV635_9591, RES_SHARED_VGA },
{ PCI_CHIP_RV635_9593, PCI_CHIP_RV635_9593, RES_SHARED_VGA },
+ { PCI_CHIP_RV635_9595, PCI_CHIP_RV635_9595, RES_SHARED_VGA },
+ { PCI_CHIP_RV635_959B, PCI_CHIP_RV635_959B, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9610, PCI_CHIP_RS780_9610, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 878fe566..b310ce89 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -265,9 +265,15 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_947B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9489, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9491, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ),
@@ -283,19 +289,27 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CD, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9504, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9506, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9508, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9509, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9517, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9519, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9555, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ),
@@ -308,12 +322,16 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV710_9592, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV630_958F, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9542, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C6, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CC, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ),
@@ -324,6 +342,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9599, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9591, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9593, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9595, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_959B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9610, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ),
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index a1b261f9..eb2e82f6 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -43,9 +43,6 @@
#include "xf86Crtc.h"
-#ifdef USE_EXA
-#include "exa.h"
-#endif
#ifdef USE_XAA
#include "xaa.h"
#endif
@@ -157,11 +154,12 @@ typedef struct _RADEONCrtcPrivateRec {
uint32_t crtc_offset;
int can_tile;
Bool enabled;
+ Bool initialized;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
uint16_t encoder_id;
- int use_count;
+ int devices;
void *dev_priv;
} radeon_encoder_rec, *radeon_encoder_ptr;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 4d743a40..0af88597 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3445,15 +3445,24 @@
#define RS690_MC_STATUS 0x90
#define RS690_MC_STATUS_IDLE (1 << 0)
-#define RS600_MC_INDEX 0x78
-# define RS600_MC_INDEX_MASK 0xff
-# define RS600_MC_INDEX_WR_EN (1 << 8)
-# define RS600_MC_INDEX_WR_ACK 0xff
-#define RS600_MC_DATA 0x7c
-
-#define RS600_MC_FB_LOCATION 0xA
-#define RS600_MC_STATUS 0x0
-#define RS600_MC_STATUS_IDLE (1 << 0)
+#define RS600_MC_INDEX 0x70
+# define RS600_MC_ADDR_MASK 0xffff
+# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
+# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
+# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
+# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
+# define RS600_MC_IND_AIC_RBS (1 << 20)
+# define RS600_MC_IND_CITF_ARB0 (1 << 21)
+# define RS600_MC_IND_CITF_ARB1 (1 << 22)
+# define RS600_MC_IND_WR_EN (1 << 23)
+#define RS600_MC_DATA 0x74
+
+#define RS600_MC_STATUS 0x0
+# define RS600_MC_IDLE (1 << 1)
+#define RS600_MC_FB_LOCATION 0x4
+#define RS600_MC_AGP_LOCATION 0x5
+#define RS600_AGP_BASE 0x6
+#define RS600_AGP_BASE2 0x7
#define AVIVO_MC_INDEX 0x0070
#define R520_MC_STATUS 0x00
@@ -3482,6 +3491,8 @@
# define R600_CHANSIZE (1 << 7)
# define R600_CHANSIZE_OVERRIDE (1 << 10)
+#define R600_SRBM_STATUS 0x0e50
+
#define AVIVO_HDP_FB_LOCATION 0x134
#define AVIVO_VGA_RENDER_CONTROL 0x0300
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index c6ed472f..f55ae12f 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1475,16 +1475,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
}
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- radeon_covering_crtc_num(pScrn,
- pPriv->drw_x,
- pPriv->drw_x + pPriv->dst_w,
- pPriv->drw_y,
- pPriv->drw_y + pPriv->dst_h,
- pPriv->desired_crtc),
- pPriv->drw_y,
- pPriv->drw_y + pPriv->dst_h,
- pPriv->vsync);
+ if (pPriv->vsync)
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
+ radeon_covering_crtc_num(pScrn,
+ pPriv->drw_x,
+ pPriv->drw_x + pPriv->dst_w,
+ pPriv->drw_y,
+ pPriv->drw_y + pPriv->dst_h,
+ pPriv->desired_crtc),
+ pPriv->drw_y,
+ pPriv->drw_y + pPriv->dst_h);
/*
* Rendering of the actual polygon is done in two different
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-17 06:34:41 +0000