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-rw-r--r--src/radeon_accel.c6
-rw-r--r--src/radeon_reg.h4
2 files changed, 6 insertions, 4 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 4ce0da62..5897c7e6 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -172,17 +172,17 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
(unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
} else {
- OUTREGP(R300_RB2D_DSTCACHE_CTLSTAT,
+ OUTREGP(R300_DSTCACHE_CTLSTAT,
R300_RB2D_DC_FLUSH_ALL,
~R300_RB2D_DC_FLUSH_ALL);
for (i = 0; i < RADEON_TIMEOUT; i++) {
- if (!(INREG(R300_RB2D_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
+ if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
break;
}
if (i == RADEON_TIMEOUT) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DC flush timeout: %x\n",
- (unsigned int)INREG(R300_RB2D_DSTCACHE_CTLSTAT));
+ (unsigned int)INREG(R300_DSTCACHE_CTLSTAT));
}
}
}
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index a9f29067..52795b16 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4686,9 +4686,11 @@
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
+#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
-#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c
+#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */
+#define R300_DSTCACHE_CTLSTAT 0x1714
# define R300_DC_FLUSH_2D (1 << 0)
# define R300_DC_FREE_2D (1 << 2)
# define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D)