diff options
| -rw-r--r-- | src/radeon.h | 6 | ||||
| -rw-r--r-- | src/radeon_driver.c | 47 | ||||
| -rw-r--r-- | src/radeon_output.c | 22 |
3 files changed, 67 insertions, 8 deletions
diff --git a/src/radeon.h b/src/radeon.h index f1b2fa3e..a3aa0746 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -837,6 +837,12 @@ extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); +extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, + RADEONSavePtr restore); +extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore); +extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore); extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 1fd71fc4..8f6ff2b2 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -4097,6 +4097,9 @@ void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); } + /* R200 DAC connected via DVO */ + if (info->ChipFamily == CHIP_FAMILY_R200) + OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); } /* Write CRTC registers */ @@ -4197,7 +4200,7 @@ void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, } -/* Write flat panel registers */ +/* Write TMDS registers */ void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -4206,10 +4209,7 @@ void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl); OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); - OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); - OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch); OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); - OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); /* old AIW Radeon has some BIOS initialization problem * with display buffer underflow, only occurs to DFP @@ -4218,8 +4218,41 @@ void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(RADEON_GRPH_BUFFER_CNTL, INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); +} + +/* Write FP2 registers */ +void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); + +} + +/* Write RMX registers */ +void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); + OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch); + +} + +/* Write LVDS registers */ +void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + if (info->IsMobility) { OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl); + /*OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);*/ OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); @@ -4654,7 +4687,10 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); + RADEONRestoreRMXRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); + RADEONRestoreFP2Registers(pScrn, restore); + RADEONRestoreLVDSRegisters(pScrn, restore); RADEONRestoreDACRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); return; @@ -4684,7 +4720,10 @@ void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); + RADEONRestoreRMXRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); + RADEONRestoreFP2Registers(pScrn, restore); + RADEONRestoreLVDSRegisters(pScrn, restore); RADEONRestoreDACRegisters(pScrn, restore); RADEONEnableOutputs(pScrn, 0); diff --git a/src/radeon_output.c b/src/radeon_output.c index 5c4a1661..55853456 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -770,9 +770,11 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); + save->lvds_pll_cntl = info->SavedReg.lvds_pll_cntl; + save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; - save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS); - save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON); + save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; + save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); if (IsPrimary) save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; @@ -862,6 +864,7 @@ static void RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & @@ -973,9 +976,20 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, switch(radeon_output->MonType) { case MT_LCD: + ErrorF("restore LVDS\n"); + if (radeon_crtc->crtc_id == 0) + RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); + RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg); case MT_DFP: - ErrorF("restore FP\n"); - RADEONRestoreFPRegisters(pScrn, &info->ModeReg); + if (radeon_crtc->crtc_id == 0) + RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); + if (radeon_output->TMDSType == TMDS_INT) { + ErrorF("restore FP\n"); + RADEONRestoreFPRegisters(pScrn, &info->ModeReg); + } else { + ErrorF("restore FP2\n"); + RADEONRestoreFP2Registers(pScrn, &info->ModeReg); + } break; default: ErrorF("restore dac\n"); |