diff options
Diffstat (limited to 'src/r600_exa.c')
| -rw-r--r-- | src/r600_exa.c | 81 |
1 files changed, 7 insertions, 74 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index 83248b3c..ea65de99 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -245,25 +245,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) cb_conf.rop = accel_state->rop; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); - BEGIN_BATCH(14); - /* Interpolator setup */ - /* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */ - EREG(accel_state->ib, SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift)); - EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); - /* color semantic id 0 -> GPR[0] */ - EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) | - (0x03 << DEFAULT_VAL_shift) | - FLAT_SHADE_bit | - SEL_CENTROID_bit)); - - /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x - * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */ - /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */ - PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3); - E32(accel_state->ib, (0 << NUM_INTERP_shift)); - E32(accel_state->ib, 0); - E32(accel_state->ib, FLAT_SHADE_ENA_bit); - END_BATCH(); + r600_set_spi(pScrn, accel_state->ib, 0, 0); /* PS alu constants */ if (accel_state->dst_obj.bpp == 16) { @@ -346,7 +328,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; - int pmask = 0; cb_config_t cb_conf; tex_resource_t tex_res; tex_sampler_t tex_samp; @@ -462,24 +443,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) cb_conf.pmask |= 8; /* A */ cb_conf.rop = accel_state->rop; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); - BEGIN_BATCH(14); - /* Interpolator setup */ - /* export tex coord from VS */ - EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); - EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); - /* color semantic id 0 -> GPR[0] */ - EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) | - (0x01 << DEFAULT_VAL_shift) | - SEL_CENTROID_bit)); - - /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x - * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */ - /* input tex coord from VS */ - PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3); - E32(accel_state->ib, ((1 << NUM_INTERP_shift))); - E32(accel_state->ib, 0); - E32(accel_state->ib, 0); - END_BATCH(); + + r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1); } @@ -1387,42 +1352,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, cb_conf.rop = 3; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); - BEGIN_BATCH(15); - /* Interpolator setup */ - if (pMask) { - /* export 2 tex coords from VS */ - EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((2 - 1) << VS_EXPORT_COUNT_shift)); - /* src = semantic id 0; mask = semantic id 1 */ - EREG(accel_state->ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | - (1 << SEMANTIC_1_shift))); - } else { - /* export 1 tex coords from VS */ - EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); - /* src = semantic id 0 */ - EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); - } - - PACK0(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); - /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ - E32(accel_state->ib, ((0 << SEMANTIC_shift) | - (0x01 << DEFAULT_VAL_shift) | - SEL_CENTROID_bit)); - /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ - E32(accel_state->ib, ((1 << SEMANTIC_shift) | - (0x01 << DEFAULT_VAL_shift) | - SEL_CENTROID_bit)); - - PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3); - if (pMask) { - /* input 2 tex coords from VS */ - E32(accel_state->ib, (2 << NUM_INTERP_shift)); - } else { - /* input 1 tex coords from VS */ - E32(accel_state->ib, (1 << NUM_INTERP_shift)); - } - E32(accel_state->ib, 0); - E32(accel_state->ib, 0); - END_BATCH(); + if (pMask) + r600_set_spi(pScrn, accel_state->ib, (2 - 1), 2); + else + r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); |