diff options
Diffstat (limited to 'src/radeon_textured_videofuncs.c')
| -rw-r--r-- | src/radeon_textured_videofuncs.c | 222 |
1 files changed, 178 insertions, 44 deletions
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index aa756f71..f5282cc2 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -106,6 +106,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv dstyoff = 0; #endif +#if 0 + ErrorF("dst_offset: 0x%x\n", dst_offset); + ErrorF("dst_pitch: 0x%x\n", dst_pitch); + ErrorF("dstxoff: 0x%x\n", dstxoff); + ErrorF("dstyoff: 0x%x\n", dstyoff); + ErrorF("src_offset: 0x%x\n", pPriv->src_offset); + ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); +#endif + if (!info->XInited3D) RADEONInit3DEngine(pScrn); @@ -122,6 +131,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv if (IS_R300_3D || IS_R500_3D) { CARD32 output_fmt; + int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) && + (info->ChipFamily != CHIP_FAMILY_RS740) && + (info->ChipFamily != CHIP_FAMILY_RS400) && + (info->ChipFamily != CHIP_FAMILY_RV515)); switch (pPixmap->drawable.bitsPerPixel) { case 16: @@ -191,36 +204,154 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txenable = R300_TEX_0_ENABLE; - BEGIN_VIDEO(7); - OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | - (0 << R300_SKIP_DWORDS_0_SHIFT) | - (0 << R300_DST_VEC_LOC_0_SHIFT) | - R300_SIGNED_0 | - (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | - (0 << R300_SKIP_DWORDS_1_SHIFT) | - (6 << R300_DST_VEC_LOC_1_SHIFT) | - R300_LAST_VEC_1 | - R300_SIGNED_1)); - OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) - << R300_WRITE_ENA_0_SHIFT) | - (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) - << R300_WRITE_ENA_1_SHIFT))); + /* setup the VAP */ + if (has_tcl) { + BEGIN_VIDEO(27); + OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0); + OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); + OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (4 << R300_PVS_NUM_FPUS_SHIFT) | + (12 << R300_VF_MAX_VTX_NUM_SHIFT))); + } else { + BEGIN_VIDEO(9); + OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); + OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (4 << R300_PVS_NUM_FPUS_SHIFT) | + (5 << R300_VF_MAX_VTX_NUM_SHIFT))); + } + + OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); + OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); + + if (has_tcl) { + OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, + ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | + (0 << R300_SKIP_DWORDS_0_SHIFT) | + (0 << R300_DST_VEC_LOC_0_SHIFT) | + R300_SIGNED_0 | + (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | + (0 << R300_SKIP_DWORDS_1_SHIFT) | + (10 << R300_DST_VEC_LOC_1_SHIFT) | + R300_LAST_VEC_1 | + R300_SIGNED_1)); + OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, + ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | + (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | + (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) + << R300_WRITE_ENA_0_SHIFT) | + (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | + (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | + (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) + << R300_WRITE_ENA_1_SHIFT))); + } else { + OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, + ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | + (0 << R300_SKIP_DWORDS_0_SHIFT) | + (0 << R300_DST_VEC_LOC_0_SHIFT) | + R300_SIGNED_0 | + (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | + (0 << R300_SKIP_DWORDS_1_SHIFT) | + (6 << R300_DST_VEC_LOC_1_SHIFT) | + R300_LAST_VEC_1 | + R300_SIGNED_1)); + OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, + ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) + << R300_WRITE_ENA_0_SHIFT) | + (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | + (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) + << R300_WRITE_ENA_1_SHIFT))); + } + + /* setup vertex shader */ + if (has_tcl) { + OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, + ((0 << R300_PVS_FIRST_INST_SHIFT) | + (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | + (1 << R300_PVS_LAST_INST_SHIFT))); + OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, + (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); + + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_ADD) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(0) | + R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | + R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_ADD) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(1) | + R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | + R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(10) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(10) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(10) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + + OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); + + OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); + OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); + OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); + OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); + OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); + } OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); - - OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); - OUT_VIDEO_REG(R300_TX_ENABLE, txenable); OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt); FINISH_VIDEO(); @@ -238,7 +369,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R300_RS_SEL_T(R300_RS_SEL_C1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1))); - OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); + OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6)); OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE); OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); OUT_VIDEO_REG(R300_US_PIXSIZE, 0); @@ -325,11 +456,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); - OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); - - OUT_VIDEO_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | - R500_RS_INST_TEX_CN_WRITE | - (0 << R500_RS_INST_TEX_ADDR_SHIFT))); + OUT_VIDEO_REG(R300_RS_INST_COUNT, 0); + OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_VIDEO_REG(R300_US_PIXSIZE, 0); OUT_VIDEO_REG(R500_US_FC_CTRL, 0); @@ -339,7 +467,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_US_CODE_RANGE_SIZE(1))); OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); - + // 7807 OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | @@ -371,10 +499,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | - R500_DY_Q_SWIZ_R)); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz + // 0x78105 OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | @@ -390,13 +519,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_RGB_ADDR1_CONST | R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | - R500_RGB_SRCP_OP_1_MINUS_2RGB0)); + R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000 OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | - R500_ALPHA_SRCP_OP_1_MINUS_2A0)); + R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000 OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | @@ -405,28 +534,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | - R500_ALU_RGB_G_SWIZ_B_1)); + R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220 OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_1)); + R500_ALPHA_SWIZ_B_1));//0x00c0c000) OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0)); + R500_ALU_RGBA_A_SWIZ_0));//0x20490000 FINISH_VIDEO(); } - BEGIN_VIDEO(4); + BEGIN_VIDEO(6); + OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); + OUT_VIDEO_REG(R300_TX_ENABLE, txenable); OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset); OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; - OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); + OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl); + OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0); + FINISH_VIDEO(); + BEGIN_VIDEO(1); OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT); FINISH_VIDEO(); |