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-rw-r--r--src/radeon_accel.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 0e0ede92..5c50cfa5 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -154,16 +154,16 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
unsigned char *RADEONMMIO = info->MMIO;
int i;
- OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT,
- RADEON_RB2D_DC_FLUSH_ALL,
- ~RADEON_RB2D_DC_FLUSH_ALL);
+ OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT,
+ RADEON_RB3D_DC_FLUSH_ALL,
+ ~RADEON_RB3D_DC_FLUSH_ALL);
for (i = 0; i < RADEON_TIMEOUT; i++) {
- if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY))
+ if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
break;
}
if (i == RADEON_TIMEOUT) {
RADEONTRACE(("DC flush timeout: %x\n",
- INREG(RADEON_RB2D_DSTCACHE_CTLSTAT)));
+ INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)));
}
}
@@ -254,8 +254,8 @@ void RADEONEngineReset(ScrnInfoPtr pScrn)
RADEON_SOFT_RESET_E2));
INREG(RADEON_RBBM_SOFT_RESET);
OUTREG(RADEON_RBBM_SOFT_RESET, 0);
- tmp = INREG(RADEON_RB2D_DSTCACHE_MODE);
- OUTREG(RADEON_RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
+ tmp = INREG(RADEON_RB3D_DSTCACHE_MODE);
+ OUTREG(RADEON_RB3D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
} else {
OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
RADEON_SOFT_RESET_CP |