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-rw-r--r--src/radeon.h1
-rw-r--r--src/radeon_crtc.c12
-rw-r--r--src/radeon_driver.c2
3 files changed, 13 insertions, 2 deletions
diff --git a/src/radeon.h b/src/radeon.h
index a5717a06..7d57ca56 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -203,6 +203,7 @@ typedef struct {
#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
#define RADEON_PLL_USE_REF_DIV (1 << 2)
+#define RADEON_PLL_LEGACY (1 << 3)
typedef struct {
CARD16 reference_freq;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5e9db39f..ea125567 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -659,6 +659,16 @@ RADEONComputePLL(RADEONPLLPtr pll,
if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
continue;
+ /* legacy radeons only have a few post_divs */
+ if (flags & RADEON_PLL_LEGACY) {
+ if ((post_div == 5) ||
+ (post_div == 7) ||
+ (post_div == 9) ||
+ (post_div == 10) ||
+ (post_div == 11))
+ continue;
+ }
+
if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
@@ -893,7 +903,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
Bool tilingOld = info->tilingEnabled;
int i = 0;
double dot_clock = 0;
- int pll_flags = 0;
+ int pll_flags = RADEON_PLL_LEGACY;
Bool update_tv_routing = FALSE;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3eecedb0..2002dd3c 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1239,7 +1239,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
pll->min_post_div = 2;
pll->max_post_div = 0x7f;
} else {
- pll->min_post_div = 2;
+ pll->min_post_div = 1;
pll->max_post_div = 12; //16 on crtc0
}
pll->min_ref_div = 2;