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-rw-r--r--src/evergreen_accel.c2
-rw-r--r--src/evergreen_exa.c28
-rw-r--r--src/evergreen_textured_videofuncs.c20
-rw-r--r--src/r600_exa.c43
-rw-r--r--src/r600_textured_videofuncs.c20
-rw-r--r--src/r6xx_accel.c2
-rw-r--r--src/radeon.h7
-rw-r--r--src/radeon_textured_video.c26
-rw-r--r--src/radeon_video.h3
9 files changed, 47 insertions, 104 deletions
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 249eff8b..7ea3c8cb 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -1472,7 +1472,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
/* sync dst surface */
evergreen_cp_set_surface_sync(pScrn, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
- accel_state->dst_size, accel_state->dst_obj.offset,
+ accel_state->dst_size, 0,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
accel_state->vbo.vb_start_op = -1;
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 6042aa48..942d7feb 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -71,7 +71,6 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
RADEON_FALLBACK(("invalid planemask\n"));
- dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
dst.surface = radeon_get_pixmap_surface(pPix);
@@ -125,7 +124,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
@@ -307,8 +306,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.pitch = accel_state->src_obj[0].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -354,7 +353,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
if (accel_state->dst_obj.bpp == 8) {
@@ -464,8 +463,6 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
accel_state->same_surface = FALSE;
- src_obj.offset = 0;
- dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.surface = radeon_get_pixmap_surface(pDst);
@@ -588,7 +585,6 @@ EVERGREENCopy(PixmapPtr pDst,
/* src to tmp */
accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
accel_state->dst_obj.bo = accel_state->copy_area_bo;
- accel_state->dst_obj.offset = 0;
accel_state->dst_obj.tiling_flags = 0;
accel_state->rop = 3;
accel_state->dst_obj.surface = NULL;
@@ -599,12 +595,10 @@ EVERGREENCopy(PixmapPtr pDst,
/* tmp to dst */
accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
accel_state->src_obj[0].bo = accel_state->copy_area_bo;
- accel_state->src_obj[0].offset = 0;
accel_state->src_obj[0].tiling_flags = 0;
accel_state->src_obj[0].surface = NULL;
accel_state->dst_obj.domain = orig_dst_domain;
accel_state->dst_obj.bo = orig_bo;
- accel_state->dst_obj.offset = 0;
accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
accel_state->rop = orig_rop;
accel_state->dst_obj.surface = orig_dst_surface;
@@ -615,7 +609,6 @@ EVERGREENCopy(PixmapPtr pDst,
/* restore state */
accel_state->src_obj[0].domain = orig_src_domain;
accel_state->src_obj[0].bo = orig_bo;
- accel_state->src_obj[0].offset = 0;
accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
accel_state->src_obj[0].surface = orig_src_surface;
} else
@@ -861,8 +854,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.pitch = accel_state->src_obj[unit].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[unit].offset;
- tex_res.mip_base = accel_state->src_obj[unit].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[unit];
tex_res.format = EVERGREENTexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
@@ -1147,8 +1140,6 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
RADEON_FALLBACK("Failed to create solid scratch pixmap\n");
}
- src_obj.offset = 0;
- dst_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.surface = radeon_get_pixmap_surface(pDst);
@@ -1177,7 +1168,6 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
RADEON_FALLBACK("Failed to create solid scratch pixmap\n");
}
}
- mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
@@ -1286,7 +1276,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.format = dst_format;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
@@ -1537,7 +1527,6 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.pitch = scratch_pitch;
src_obj.width = w;
src_obj.height = h;
- src_obj.offset = 0;
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
@@ -1547,7 +1536,6 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
dst_obj.height = pDst->drawable.height;
- dst_obj.offset = 0;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
@@ -1678,7 +1666,6 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
src_obj.pitch = src_pitch_hw;
src_obj.width = pSrc->drawable.width;
src_obj.height = pSrc->drawable.height;
- src_obj.offset = 0;
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
@@ -1688,7 +1675,6 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
dst_obj.height = h;
- dst_obj.offset = 0;
dst_obj.bo = scratch;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 2ffcdbed..1ae0ae2f 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -152,8 +152,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (vs_const_conf);
CLEAR (ps_const_conf);
- dst_obj.offset = 0;
- src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
@@ -243,8 +241,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.pitch = accel_state->src_obj[0].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -290,8 +288,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
- tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
- tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
+ tex_res.base = pPriv->planev_offset;
+ tex_res.mip_base = pPriv->planev_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.array_mode = 1;
@@ -313,8 +311,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
- tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
- tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
+ tex_res.base = pPriv->planeu_offset;
+ tex_res.mip_base = pPriv->planeu_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.array_mode = 1;
@@ -336,8 +334,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -379,7 +377,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 9a976d3e..61b6315c 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -52,7 +52,7 @@ R600SetAccelState(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- uint32_t pitch_align = 0x7, base_align = 0xff;
+ uint32_t pitch_align = 0x7;
int ret;
if (src0) {
@@ -65,10 +65,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
if (accel_state->src_obj[0].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
- /* bad offset */
- if (accel_state->src_obj[0].offset & base_align)
- RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[0].offset));
-
} else {
memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = 0;
@@ -85,9 +81,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
if (accel_state->src_obj[1].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
- /* bad offset */
- if (accel_state->src_obj[1].offset & base_align)
- RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[1].offset));
} else {
memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
accel_state->src_size[1] = 0;
@@ -105,8 +98,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
if (accel_state->dst_obj.pitch & pitch_align)
RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
- if (accel_state->dst_obj.offset & base_align)
- RADEON_FALLBACK(("Bad dst offset 0x%08x\n", accel_state->dst_obj.offset));
} else {
memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
accel_state->dst_size = 0;
@@ -159,7 +150,6 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
RADEON_FALLBACK(("invalid planemask\n"));
- dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
dst.surface = radeon_get_pixmap_surface(pPix);
@@ -212,7 +202,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
@@ -387,8 +377,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.pitch = accel_state->src_obj[0].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -435,7 +425,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
if (accel_state->dst_obj.bpp == 8) {
@@ -544,8 +534,6 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
accel_state->same_surface = FALSE;
- src_obj.offset = 0;
- dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
@@ -653,7 +641,6 @@ R600Copy(PixmapPtr pDst,
RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
if (accel_state->same_surface && accel_state->copy_area) {
- uint32_t orig_offset, tmp_offset;
uint32_t orig_dst_domain = accel_state->dst_obj.domain;
uint32_t orig_src_domain = accel_state->src_obj[0].domain;
uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
@@ -661,13 +648,9 @@ R600Copy(PixmapPtr pDst,
struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
int orig_rop = accel_state->rop;
- tmp_offset = 0;
- orig_offset = 0;
-
/* src to tmp */
accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
accel_state->dst_obj.bo = accel_state->copy_area_bo;
- accel_state->dst_obj.offset = tmp_offset;
accel_state->dst_obj.tiling_flags = 0;
accel_state->rop = 3;
R600DoPrepareCopy(pScrn);
@@ -677,11 +660,9 @@ R600Copy(PixmapPtr pDst,
/* tmp to dst */
accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
accel_state->src_obj[0].bo = accel_state->copy_area_bo;
- accel_state->src_obj[0].offset = tmp_offset;
accel_state->src_obj[0].tiling_flags = 0;
accel_state->dst_obj.domain = orig_dst_domain;
accel_state->dst_obj.bo = orig_bo;
- accel_state->dst_obj.offset = orig_offset;
accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
accel_state->rop = orig_rop;
R600DoPrepareCopy(pScrn);
@@ -691,7 +672,6 @@ R600Copy(PixmapPtr pDst,
/* restore state */
accel_state->src_obj[0].domain = orig_src_domain;
accel_state->src_obj[0].bo = orig_bo;
- accel_state->src_obj[0].offset = orig_offset;
accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
} else
R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
@@ -890,8 +870,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.pitch = accel_state->src_obj[unit].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[unit].offset;
- tex_res.mip_base = accel_state->src_obj[unit].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[unit];
tex_res.format = R600TexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
@@ -1205,8 +1185,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
RADEON_FALLBACK("Failed to create solid scratch pixmap\n");
}
- src_obj.offset = 0;
- dst_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
@@ -1237,7 +1215,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
}
- mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
mask_obj.surface = radeon_get_pixmap_surface(pMask);
@@ -1344,7 +1321,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.format = dst_format;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
@@ -1581,7 +1558,6 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.pitch = scratch_pitch;
src_obj.width = w;
src_obj.height = h;
- src_obj.offset = 0;
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
@@ -1591,7 +1567,6 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
dst_obj.height = pDst->drawable.height;
- dst_obj.offset = 0;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
@@ -1718,7 +1693,6 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
src_obj.pitch = src_pitch_hw;
src_obj.width = pSrc->drawable.width;
src_obj.height = pSrc->drawable.height;
- src_obj.offset = 0;
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
@@ -1728,7 +1702,6 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
dst_obj.height = h;
- dst_obj.offset = 0;
dst_obj.bo = scratch;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index a4a67f2a..970ab8e6 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -164,8 +164,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (vs_conf);
CLEAR (ps_conf);
- dst_obj.offset = 0;
- src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
@@ -259,8 +257,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.pitch = accel_state->src_obj[0].pitch;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -307,8 +305,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
- tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
- tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
+ tex_res.base = pPriv->planev_offset;
+ tex_res.mip_base = pPriv->planev_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
@@ -330,8 +328,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dst_sel_w = SQ_SEL_1;
tex_res.interlaced = 0;
- tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
- tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
+ tex_res.base = pPriv->planeu_offset;
+ tex_res.mip_base = pPriv->planeu_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
if (accel_state->src_obj[0].tiling_flags == 0)
tex_res.tile_mode = 1;
@@ -353,8 +351,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
- tex_res.base = accel_state->src_obj[0].offset;
- tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.base = 0;
+ tex_res.mip_base = 0;
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -397,7 +395,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
- cb_conf.base = accel_state->dst_obj.offset;
+ cb_conf.base = 0;
cb_conf.bo = accel_state->dst_obj.bo;
cb_conf.surface = accel_state->dst_obj.surface;
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 5fe643dd..eb0241c7 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -1233,7 +1233,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
/* sync dst surface */
r600_cp_set_surface_sync(pScrn, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
- accel_state->dst_size, accel_state->dst_obj.offset,
+ accel_state->dst_size, 0,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
accel_state->vbo.vb_start_op = -1;
diff --git a/src/radeon.h b/src/radeon.h
index 46263686..9efe5d1c 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -297,7 +297,6 @@ struct r600_accel_object {
uint32_t pitch;
uint32_t width;
uint32_t height;
- uint32_t offset;
int bpp;
uint32_t domain;
struct radeon_bo *bo;
@@ -439,12 +438,6 @@ typedef struct {
void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL);
-#ifdef ARGB_CURSOR
- Bool cursor_argb;
-#endif
- int cursor_fg;
- int cursor_bg;
-
int pix24bpp; /* Depth of pixmap for 24bpp fb */
Bool dac6bits; /* Use 6 bit DAC? */
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 1a0d51d2..80650c31 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -257,24 +257,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
if (pPriv->video_memory == NULL) {
- pPriv->video_offset = radeon_legacy_allocate_memory(pScrn,
- &pPriv->video_memory,
- size, pPriv->hw_align,
- RADEON_GEM_DOMAIN_GTT);
- if (pPriv->video_offset == 0)
- return BadAlloc;
-
- pPriv->src_bo[0] = pPriv->video_memory;
- radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size,
- pPriv->hw_align,
- RADEON_GEM_DOMAIN_GTT);
+ int ret;
+ ret = radeon_legacy_allocate_memory(pScrn,
+ &pPriv->video_memory,
+ size, pPriv->hw_align,
+ RADEON_GEM_DOMAIN_GTT);
+ if (ret == 0)
+ return BadAlloc;
+
+ pPriv->src_bo[0] = pPriv->video_memory;
+ radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size,
+ pPriv->hw_align,
+ RADEON_GEM_DOMAIN_GTT);
}
/* Bicubic filter loading */
if (pPriv->bicubic_enabled) {
if (info->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
- pPriv->bicubic_src_offset = info->bicubic_offset;
}
if (pDraw->type == DRAWABLE_WINDOW)
@@ -291,8 +291,6 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
top = (y1 >> 16) & ~1;
nlines = ((y2 + 0xffff) >> 16) - top;
- pPriv->src_offset = pPriv->video_offset;
-
pPriv->currentBuffer ^= 1;
src_bo = pPriv->src_bo[pPriv->currentBuffer];
diff --git a/src/radeon_video.h b/src/radeon_video.h
index e2bfd6f7..463f91d9 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -31,14 +31,12 @@ typedef struct {
int size;
void *video_memory;
- int video_offset;
int planeu_offset;
int planev_offset;
/* bicubic filtering */
Bool bicubic_enabled;
- uint32_t bicubic_src_offset;
int bicubic_state;
#define BICUBIC_OFF 0
#define BICUBIC_ON 1
@@ -49,7 +47,6 @@ typedef struct {
DrawablePtr pDraw;
PixmapPtr pPixmap;
- uint32_t src_offset;
uint32_t src_pitch;
uint8_t *src_addr;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 04:48:54 +0000