diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/drmmode_display.c | 3 | ||||
| -rw-r--r-- | src/radeon_exa.c | 18 | ||||
| -rw-r--r-- | src/radeon_exa_funcs.c | 46 |
3 files changed, 38 insertions, 29 deletions
diff --git a/src/drmmode_display.c b/src/drmmode_display.c index 2ab4510c..d5ad211a 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -1232,8 +1232,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) } #endif if (tiling_flags) - radeon_bo_set_tiling(info->front_bo, - tiling_flags | RADEON_TILING_SURFACE, pitch); + radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth, scrn->bitsPerPixel, pitch, diff --git a/src/radeon_exa.c b/src/radeon_exa.c index 9df7251e..3dbdcae4 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -307,6 +307,7 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index) #endif Bool flush = FALSE; int ret; + uint32_t tiling_flags = 0, pitch = 0; #if X_BYTE_ORDER == X_BIG_ENDIAN /* May need to handle byte swapping in DownloadFrom/UploadToScreen */ @@ -318,16 +319,13 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index) if (!driver_priv) return FALSE; - if (info->ChipFamily >= CHIP_FAMILY_R600) { - uint32_t tiling_flags = 0, pitch = 0; - - ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch); - if (ret) - return FALSE; - /* untile in DFS/UTS */ - if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)) - return FALSE; - } + /* check if we are tiled */ + ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch); + if (ret) + return FALSE; + /* untile in DFS/UTS */ + if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)) + return FALSE; /* if we have more refs than just the BO then flush */ if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index e80a9967..e8c55718 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -474,6 +474,7 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, Bool flush = TRUE; Bool r; int i; + uint32_t tiling_flags = 0, pitch = 0; if (bpp < 8) return FALSE; @@ -482,6 +483,10 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, if (!driver_priv || !driver_priv->bo) return FALSE; + ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch); + if (ret) + ErrorF("radeon_bo_get_tiling failed\n"); + #if X_BYTE_ORDER == X_BIG_ENDIAN switch (bpp) { case 32: @@ -496,10 +501,12 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, /* If we know the BO won't be busy, don't bother with a scratch */ copy_dst = driver_priv->bo; copy_pitch = pDst->devKind; - if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { - flush = FALSE; - if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain)) - goto copy; + if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { + if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { + flush = FALSE; + if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain)) + goto copy; + } } size = scratch_pitch * h; @@ -573,6 +580,7 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, int ret; Bool flush = FALSE; Bool r; + uint32_t tiling_flags = 0, pitch = 0; if (bpp < 8) return FALSE; @@ -581,6 +589,10 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, if (!driver_priv || !driver_priv->bo) return FALSE; + ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch); + if (ret) + ErrorF("radeon_bo_get_tiling failed\n"); + #if X_BYTE_ORDER == X_BIG_ENDIAN switch (bpp) { case 32: @@ -595,22 +607,22 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ copy_src = driver_priv->bo; copy_pitch = pSrc->devKind; - if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { - src_domain = radeon_bo_get_src_domain(driver_priv->bo); - if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == - (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) - src_domain = 0; - else /* A write may be scheduled */ - flush = TRUE; - } + if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { + if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { + src_domain = radeon_bo_get_src_domain(driver_priv->bo); + if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == + (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) + src_domain = 0; + else /* A write may be scheduled */ + flush = TRUE; + } - if (!src_domain) - radeon_bo_is_busy(driver_priv->bo, &src_domain); + if (!src_domain) + radeon_bo_is_busy(driver_priv->bo, &src_domain); - if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) { - goto copy; + if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) + goto copy; } - size = scratch_pitch * h; scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { |