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-rw-r--r--src/radeon_exa.c4
-rw-r--r--src/radeon_exa_funcs.c18
-rw-r--r--src/radeon_exa_render.c30
3 files changed, 24 insertions, 28 deletions
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 2c36882c..d99bf377 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -531,14 +531,10 @@ Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
#define LEAVE_DRAW(x) TRACE
/***********************************************************************/
-#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
-#define OUT_RELOC(x, read, write) OUT_RING_RELOC(x, read, write)
-
#ifdef RENDER
#include "radeon_exa_render.c"
#endif
#include "radeon_exa_funcs.c"
-#undef BEGIN_ACCEL
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 759cac1a..288f9364 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -80,11 +80,11 @@ static void Emit2DState(ScrnInfoPtr pScrn, int op)
OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
- OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ OUT_RING_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
if (has_src) {
OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
- OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
+ OUT_RING_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
}
ADVANCE_RING();
@@ -100,7 +100,7 @@ RADEONFlush2D(PixmapPtr pPix)
TRACE;
- BEGIN_ACCEL(2);
+ BEGIN_RING(2*2);
OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
OUT_RING_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
@@ -191,7 +191,7 @@ RADEONSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
radeon_pick_best_crtc(pScrn, x1, x2, y1, y2),
y1, y2);
- BEGIN_ACCEL(2);
+ BEGIN_RING(2*2);
OUT_RING_REG(RADEON_DST_Y_X, (y1 << 16) | x1);
OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
ADVANCE_RING();
@@ -304,7 +304,7 @@ RADEONCopy(PixmapPtr pDst,
radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
dstY, dstY + h);
- BEGIN_ACCEL(3);
+ BEGIN_RING(2*3);
OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
@@ -328,7 +328,7 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
} else if (src_bo && dst_bo == NULL) {
BEGIN_ACCEL_RELOC(6, 1);
} else {
- BEGIN_ACCEL(6);
+ BEGIN_RING(2*6);
}
OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL,
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
@@ -342,17 +342,17 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
RADEON_GMC_WR_MSK_DIS);
OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset);
if (src_bo) {
- OUT_RELOC(src_bo, src_domain, 0);
+ OUT_RING_RELOC(src_bo, src_domain, 0);
}
OUT_RING_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
if (dst_bo) {
- OUT_RELOC(dst_bo, 0, dst_domain);
+ OUT_RING_RELOC(dst_bo, 0, dst_domain);
}
OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
ADVANCE_RING();
- BEGIN_ACCEL(2);
+ BEGIN_RING(2*2);
OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
OUT_RING_REG(RADEON_WAIT_UNTIL,
RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 6d61a805..c673f2c7 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1278,7 +1278,7 @@ static Bool R300TextureSetup(PicturePtr pPict, PixmapPtr pPix,
if (info->accel_state->has_tcl) {
info->accel_state->texW[unit] = 1;
info->accel_state->texH[unit] = 1;
- BEGIN_ACCEL(9);
+ BEGIN_RING(2*9);
if (IS_R300_3D)
OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_CONST_INDEX(unit * 2));
else
@@ -1307,7 +1307,7 @@ static Bool R300TextureSetup(PicturePtr pPict, PixmapPtr pPix,
info->accel_state->texW[unit] = 1;
info->accel_state->texH[unit] = 1;
- BEGIN_ACCEL(9);
+ BEGIN_RING(2*9);
if (IS_R300_3D)
OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_CONST_INDEX(unit * 2));
else
@@ -1499,15 +1499,15 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
/* setup the VAP */
if (info->accel_state->has_tcl) {
if (pMask)
- BEGIN_ACCEL(10);
+ BEGIN_RING(2*10);
else
- BEGIN_ACCEL(9);
+ BEGIN_RING(2*9);
OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
} else {
if (pMask)
- BEGIN_ACCEL(6);
+ BEGIN_RING(2*6);
else
- BEGIN_ACCEL(5);
+ BEGIN_RING(2*5);
}
/* These registers define the number, type, and location of data submitted
@@ -1670,7 +1670,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
/* setup the rasterizer, load FS */
if (pMask) {
- BEGIN_ACCEL(16);
+ BEGIN_RING(2*16);
/* 4 components: 2 for tex0, 2 for tex1 */
OUT_RING_REG(R300_RS_COUNT,
((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1693,7 +1693,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
} else {
- BEGIN_ACCEL(15);
+ BEGIN_RING(2*15);
/* 2 components: 2 for tex0 */
OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1865,7 +1865,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
mask_alpha = R500_ALPHA_SWIZ_B_1;
}
- BEGIN_ACCEL(7);
+ BEGIN_RING(2*7);
if (pMask) {
/* 4 components: 2 for tex0, 2 for tex1 */
OUT_RING_REG(R300_RS_COUNT,
@@ -1899,7 +1899,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
ADVANCE_RING();
if (pMask) {
- BEGIN_ACCEL(19);
+ BEGIN_RING(2*19);
OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst for src texture */
OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
@@ -1971,7 +1971,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
} else {
- BEGIN_ACCEL(13);
+ BEGIN_RING(2*13);
OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst for src texture */
OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
@@ -2064,7 +2064,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
}
/* Clear out scissoring */
- BEGIN_ACCEL(2);
+ BEGIN_RING(2*2);
if (IS_R300_3D) {
OUT_RING_REG(R300_SC_SCISSOR0, ((1440 << R300_SCISSOR_X_SHIFT) |
(1440 << R300_SCISSOR_Y_SHIFT)));
@@ -2089,7 +2089,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
ADVANCE_RING();
- BEGIN_ACCEL(1);
+ BEGIN_RING(2*1);
if (pMask)
OUT_RING_REG(R300_VAP_VTX_SIZE, 6);
else
@@ -2134,11 +2134,11 @@ static void RadeonFinishComposite(PixmapPtr pDst)
}
if (IS_R300_3D || IS_R500_3D) {
- BEGIN_ACCEL(3);
+ BEGIN_RING(2*3);
OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
} else
- BEGIN_ACCEL(1);
+ BEGIN_RING(2*1);
OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
ADVANCE_RING();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 08:14:08 +0000