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2012-05-24radeon: update compat-api.h for block handler + enable/disable fb.Dave Airlie
This updates the compat stuff for the latest block handler code, and the enable/disable interface. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-24radeon/xvmc: fix build with new API.Dave Airlie
This was missing the compat include. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-24radeon: fix a few more RHDAtomBiosFunc usesDave Airlie
I missed these in my initial search/replace for some reason. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-24radeon/atombios: rewrite atombios parser code to not use xf86Screens.Dave Airlie
Just pass the ScrnInfoPtr around instead. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-24radeon/generic_bus: stop passing scrnIndexDave Airlie
Just pass a pointer to the screen, removes usage of xf86Screens lookup Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23compat for new server APIDave Airlie
2012-05-23ati: convert to new screen conversion APIsDave Airlie
The compat header takes care of the old server vs new server. this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23radeon: add compat-api.hDave Airlie
2012-05-23radeon/xaa: drop scrnIndex parameter to some functionsDave Airlie
This isn't needed, and makes api changes later easier. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-16UMS/EXA: Add reminder for potential solid picture performance issue.Thierry Vignaud
2012-05-11radeon: use GB_GR and BG_RG formats for packed yuv video for r600+Roland Scheidegger
Those formats were invented for exactly that purpose so use them. This saves some code and also some hw resources (only need one sampler instead of two for packed yuv). Only tested on EG.
2012-05-11radeon: avoid rounding errors in texture coords for textured xv on EG+Roland Scheidegger
make sure the division is done with floats, otherwise the coordinate can be wrong up to 1 texel. Particularly visible with clipping and small source scaled up (since one texel can be a shift of several pixels) but could be seen even unscaled. Should provide more accurate coords without clipping too depending on the scale factor probably. This is a straight port of 688c8a54a00b01e73a11970ad2abe858f8c7c5c4 when I apparently forgot the eg code...
2012-05-10Fail more gracefully when drm surface manager can't be initializedAnisse Astier
Should make bugs like https://bugs.freedesktop.org/show_bug.cgi?id=48138 easier to diagnose. [ Michel Dänzer: Appended newline to error message. ] Signed-off-by: Anisse Astier <anisse@astier.eu> Singed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-09EXA/UMS: Synchronize to the GPU before writing solid colour to scratch pixmap.Michel Dänzer
UMS doesn't do this automagically. It's a big hammer that will probably suck for performance, but I don't have any better ideas right now. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-03EXA: Attempt to fix solid picture acceleration with UMS.Michel Dänzer
Only compile tested, but should fix https://bugs.freedesktop.org/show_bug.cgi?id=49182 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-02radeon: add MacModel entry for SAM440ep embedded boardAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-04-16EXA: Support acceleration of solid pictures on R2xx.Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-04-16EXA: Support acceleration of solid pictures on R1xx.Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-04-16EXA: Support acceleration of solid pictures on Evergreen/NI.Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-04-16EXA: Support acceleration of solid pictures on R3xx-R7xx.Michel Dänzer
Allocate 1x1 scratch pixmaps to hold the solid picture colours. This works around https://bugs.freedesktop.org/show_bug.cgi?id=47266 and might improve performance in other cases as well. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-04-16RADEONCopySwap: Fix RADEON_HOST_DATA_SWAP_16BIT case.Michel Dänzer
It was the same code as for RADEON_HOST_DATA_SWAP_32BIT. This caused bus errors on FreeBSD/PPC, but I'm not sure how it could not cause problems anywhere... Reported-by: Andreas Tobler <andreast@fgznet.ch> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-04-16Make radeon_setup_kernel_mem failures more graceful and verbose.Michel Dänzer
So that bugs like https://bugs.freedesktop.org/show_bug.cgi?id=48138 can be diagnosed more easily. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-04-05r6xx-r9xx: force 1D tiling for buffer with height < 64Jerome Glisse
Due to some old kernel issue, height is 8 aligned insided the ddx For buffer with height btw 57 & 63 this lead ddx to believe it can allocate a 2D tiled surface while mesa will not align height and will assume 1D tiled leading to disagreement and rendering issue. This patch force buffer with height < 64 to be 1D tiled. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-03-29configure: bump version post releaseAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-29configure: bump version for releasexf86-video-ati-6.14.4Alex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-28configure: bump libdrm requirement for TN supportAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-27radeon: man page updatesAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-20radeon/kms: add TN pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-20radeon/kms: add support for TN (trinity) APUsAlex Deucher
- KMS only - Includes full EXA/Xv support Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-07r6xx: initialize SX_MISCMarek Olšák
If Mesa set it to 1, the DDX would not render anything = the monitor would basically freeze. agd5f: update emit count as well. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-03-06DRI2: Unreference buffers immediately when event wait info is invalidated.Michel Dänzer
Deferring this could result in trying to unreference buffers from a previous server generation, i.e. accessing freed memory. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Christian König <Christian.koenig@amd.com>
2012-03-06Re-register DRM FD wakeup handler for each server generation.Michel Dänzer
Fixes hang when trying to use DRI2 swap scheduling after a server reset. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Christian König <Christian.koenig@amd.com>
2012-02-24Fix ConnectorTable crash in radeon_output.cHans Verkuil
The sam440ep PPC board requires a ConnectorTable xorg.conf option, but putting in that option causes the radeon driver to crash. I finally traced it to a copy-and-paste bug in radeon_output.c as a result of a major rework in commit 82f12e5a40c1fbcb91910a0f8b725c34fff02aae. The actual crash occurred in RADEONPrintPortMap(). Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-20radeon: avoid rounding errors in texture coords for textured xvRoland Scheidegger
make sure the division is done with floats, otherwise the coordinate can be wrong up to 1 texel. Particularly visible with clipping and small source scaled up (since one texel can be a shift of several pixels) but could be seen even unscaled. Should provide more accurate coords without clipping too depending on the scale factor probably. Changed for r100-r600, though only tested on r300.
2012-02-13radeon: r6xx-eg use linear general when using scratch boJerome Glisse
In path where we need to use scratch bo as temporary area, consider it as linear buffer. Not linear aligned. Fix some case such as in bugs: https://bugs.freedesktop.org/show_bug.cgi?id=45827 Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-13Handle new xorg_list API.Michel Dänzer
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45937 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-10radeon: fix crash in drmmode_create_bo_pixmap()Alex Deucher
Only init surface on r6xx+. Return NULL rather than FALSE. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=45829 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-10radeon/kms: reusing fd message is not an errorAlex Deucher
It's standard behavior. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-08EXA/r6xx+: Only set write domain or read domains, not both. (Bug #43893)Michel Dänzer
Avoids an accounting bug in libdrm_radeon 2.4.31 or older. See https://bugs.freedesktop.org/show_bug.cgi?id=43893 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08Fix UMS build failure.Michel Dänzer
And some UMS specific warnings. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08Remove unused local variable 'height'.Michel Dänzer
Pointed out by gcc -Wunused-variable. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08evergreen: Initialize source surface member for textured video.Michel Dänzer
Fixes crash reported by Ole Salscheider on IRC. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-07radeon: fix tiling for weird resolutionJerome Glisse
Should also fix xv for some case. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01Fix vline range calculations.Michel Dänzer
The range passed in is in pixmap coordinates, so the CRTC offset needs to be added to the clamping limits and subtracted from the clamped range for pre-AVIVO display engines. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-01Check for empty vline ranges after clamping.Michel Dänzer
The clamping could turn a previously non-empty range into an empty one. Also, start == stop means the range is empty. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-01-10EXA/r6xx+: fix rop setting for overlapping copiesAlex Deucher
Need to use GXCopy for the src to temp copy, then the original rop for the temp to dest copy. Noticed by: Frank Huang Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-05DPMS: Split non-modeset CRTC DPMS function.Egbert Eich
RADEONRestore() calls crtc->funcs->dpms() after most of the mode setting subsystems have been restored. This function enables the CRTCs but does more: it calls DRM pre- and post-modeset ioctls and sets up the palettes (LUTs). None of these two things are needed. Accessing the palette registers after restoring the PLLs can even lead to lockups. Thus the CRTC DPMS function is split into two parts: one that just enables /disables the CRTC and one which wraps this function and does the rest. Now the inner function can be called directly from RADEONRestore() as there is no need to go thru the RandR hooks in this function while the RandR hook uses the wrappering function so the full functionality is preserved from an RandR point of view. Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-05UMS: Fix lockups in palette save/restore on pre-AVIVO chips.Egbert Eich
The reintroduction of palette save/restore in 5efdf514 causes some pre-AVIVO chips to lock up. An investigation revealed that accessing palette registers when the associated PLL is not running is causing this. With UMS the PLL setup that is saved has been done by the BIOS typically. A similar issue was observed when VGA palette save/restore had been reinitroduced with 80eee856: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=480312 and has been worked around for Linux without further investigation by 87e66ce7. To fix the issue we now a. introduce 'on-demand' palette saving (ie the palette is saved before it is first altered). This guarantees that the palette register are only associated when the associated CRTC is active and thus the PLLs are powered up and running. b. move palette restore before PLL restore. c. eliminate generic VGA palette save/restore which seems to be unneeded when the palette is restored natively. It is believed that this caused the behavior described in https://bugs.freedesktop.org/show_bug.cgi?id=18407#c27 Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-02Update for new vgaHW API.Matthieu Herrb
Signed-off-by: Matthieu Herrb <matthieu.herrb@laas.fr> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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