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AgeCommit message (Collapse)Author
2012-02-13radeon: r6xx-eg use linear general when using scratch boJerome Glisse
In path where we need to use scratch bo as temporary area, consider it as linear buffer. Not linear aligned. Fix some case such as in bugs: https://bugs.freedesktop.org/show_bug.cgi?id=45827 Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-13Handle new xorg_list API.Michel Dänzer
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45937 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-10radeon: fix crash in drmmode_create_bo_pixmap()Alex Deucher
Only init surface on r6xx+. Return NULL rather than FALSE. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=45829 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-10radeon/kms: reusing fd message is not an errorAlex Deucher
It's standard behavior. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-08EXA/r6xx+: Only set write domain or read domains, not both. (Bug #43893)Michel Dänzer
Avoids an accounting bug in libdrm_radeon 2.4.31 or older. See https://bugs.freedesktop.org/show_bug.cgi?id=43893 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08Fix UMS build failure.Michel Dänzer
And some UMS specific warnings. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08Remove unused local variable 'height'.Michel Dänzer
Pointed out by gcc -Wunused-variable. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-08evergreen: Initialize source surface member for textured video.Michel Dänzer
Fixes crash reported by Ole Salscheider on IRC. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-07radeon: fix tiling for weird resolutionJerome Glisse
Should also fix xv for some case. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01Fix vline range calculations.Michel Dänzer
The range passed in is in pixmap coordinates, so the CRTC offset needs to be added to the clamping limits and subtracted from the clamped range for pre-AVIVO display engines. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-01Check for empty vline ranges after clamping.Michel Dänzer
The clamping could turn a previously non-empty range into an empty one. Also, start == stop means the range is empty. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-01-10EXA/r6xx+: fix rop setting for overlapping copiesAlex Deucher
Need to use GXCopy for the src to temp copy, then the original rop for the temp to dest copy. Noticed by: Frank Huang Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-05DPMS: Split non-modeset CRTC DPMS function.Egbert Eich
RADEONRestore() calls crtc->funcs->dpms() after most of the mode setting subsystems have been restored. This function enables the CRTCs but does more: it calls DRM pre- and post-modeset ioctls and sets up the palettes (LUTs). None of these two things are needed. Accessing the palette registers after restoring the PLLs can even lead to lockups. Thus the CRTC DPMS function is split into two parts: one that just enables /disables the CRTC and one which wraps this function and does the rest. Now the inner function can be called directly from RADEONRestore() as there is no need to go thru the RandR hooks in this function while the RandR hook uses the wrappering function so the full functionality is preserved from an RandR point of view. Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-05UMS: Fix lockups in palette save/restore on pre-AVIVO chips.Egbert Eich
The reintroduction of palette save/restore in 5efdf514 causes some pre-AVIVO chips to lock up. An investigation revealed that accessing palette registers when the associated PLL is not running is causing this. With UMS the PLL setup that is saved has been done by the BIOS typically. A similar issue was observed when VGA palette save/restore had been reinitroduced with 80eee856: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=480312 and has been worked around for Linux without further investigation by 87e66ce7. To fix the issue we now a. introduce 'on-demand' palette saving (ie the palette is saved before it is first altered). This guarantees that the palette register are only associated when the associated CRTC is active and thus the PLLs are powered up and running. b. move palette restore before PLL restore. c. eliminate generic VGA palette save/restore which seems to be unneeded when the palette is restored natively. It is believed that this caused the behavior described in https://bugs.freedesktop.org/show_bug.cgi?id=18407#c27 Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-02Update for new vgaHW API.Matthieu Herrb
Signed-off-by: Matthieu Herrb <matthieu.herrb@laas.fr> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-12-28DRI2: Can't use page flipping for pixmaps. (bug #42913)Michel Dänzer
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=42913 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-12-12radeon: add some new pci idsAlex Deucher
fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43739 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-12-06radeon: add original radeon to always tiled.Dave Airlie
and actually enable it for M7, previous commit only did one function. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-06radeon: refine always tiled depth checkDave Airlie
So it appears the M7 family always tiles its depth buffer also. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-05radeon: r200 depth buffers are always tiledDave Airlie
When we do the allocations we need to make sure the always tiled nature is taken into account. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-05Xv: Evergreen+ asics support 16k surfacesAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-12-01radeon: add some new pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-11-28fixup xinerama since 9151f3b1c2ebcc34e63195888ba696f2183ba5e2Dave Airlie
since the driver would call RRFirstOutput without checking if randr has been enabled, and it would crash in privates code. reported by vereteran on #radeon Signed-off-by: Dave Airlie <airlied@redhat.com> Acked-on-irc-by: Michel Dänzer <michel.daenzer@amd.com>
2011-11-21ddx/evergreen: Fix endian of ALU constantsBenjamin Herrenschmidt
The constants are written directly into a buffer object shared with the card and we "forget" to swap them. This patch fixes it by doing the swap in evergreen_set_alu_consts() in-place (ie, it modifies the buffer), which should be fine with the way we use it in the ddx. This makes everything work fine on my caicos card on a G5 including some quik tests with Xv, gnome3 shell, etc... Thanks a lot to Jerome Glisse for holding my hand through debugging that (and finding the actual bug). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-11-14radeon: add missing FireMV pci idAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-11-11ati: enable bg none when fbcon succeeds and we are built against ABI after 10.Dave Airlie
One less patch to keep carrying in Fedora. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-08UMS: Guard references to PCITAG / pciTag with XSERVER_LIBPCIACCESS (bug #42690)Michel Dänzer
Should fix https://bugs.freedesktop.org/show_bug.cgi?id=42690 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-11-04DRI/DRI2: remove hard-coded limitation to 6 crtcsIlija Hadzic
DRM's hard limit to the number of CRTCs is 32. ATI DDX unnecessarily clips this limit to 6 by hard coding initial assumption for output->possible_crtcs mask to 0x7f (before it gets trimmed down to what's really possible for a given output) and by allocating only 6 entries for for cursor_bo[] array in RADEONInfoRec. Fix this and thus allow the ATI DDX to deal with as many CRTCs as the DRM allows (32), so it is ready if anything with >6 CRTCs comes out. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
2011-11-04Turn compile time check into runtime check.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-11-04check for xserver 1.9.4.901 to enable tiling by defaultAlex Deucher
Previous xservers had a bug in the EXA code which caused display corruption in some cases. See: https://bugs.freedesktop.org/show_bug.cgi?id=33929 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-11-02Bump version post release.Michel Dänzer
2011-11-02Bump version for 6.14.3 release.xf86-video-ati-6.14.3Michel Dänzer
2011-11-01Build fix for -Werror=int-to-pointer-castJeremy Huddleston
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2011-10-31radeon: do not include xf86PciInfo.hTormod Volden
We already use atipciids.h instead most places. Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
2011-10-29Use malloc/calloc/realloc/free directlyJeremy Huddleston
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2011-10-27EXA >= R6xx / KMS: Avoid running out of CS space at inconvenient times.Michel Dänzer
Otherwise we may end up with things not properly set up at the beginning of the next CS. Fixes http://bugs.debian.org/645007 . In contrast to the Composite code for < R6xx, this isn't necessary with UMS, as the draw packet only uses constant space in the indirect buffer, and nothing else can mess with the 3D state between indirect buffers. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-10-27EXA < R6xx: Make sure 2D state is re-emitted after running out of CS space.Michel Dänzer
Otherwise it's basically luck what the 2D state ends up being at the beginning of the next CS. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-10-25Make radeon_dri2_create_buffer(s) more robust. (Bug #30047)Michel Dänzer
In particular, handle and propagate failure to allocate GPU accessible memory, instead of crashing. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=30047 . Also take care not to leak resources in error paths. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-10-20radeon/kms: fallback to vesa if GPU is not supported by UMSJerome Glisse
For GPU not supported by UMS, test in probe so that we properly fallback to vesa. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-10-19dri2: Add vdpau driver name entryMaarten Lankhorst
libvdpau has a driver loading mechanism that looks for a dri2 driver first before falling back to nvidia, so lets use that. Allows use of libvdpau_rx00 without having to set things up separately, similar to the patch to xf86-video-nouveau. Signed-off-by: Maarten Lankhorst <m.b.lankhorst@gmail.com> Reviewed-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Michel Dänzer <michel@daenzer.net> Tested-by: Michel Dänzer <michel@daenzer.net>
2011-09-22UMS: fix DDIA enable on some rs690 systemsAlex Deucher
DVOOutputControl checks the value of of bios scratch reg 3 on some tables and assumes the encoder is already enabled if the DFP2_ACTIVE bit is set. Clear that bit so the table sets the DDIA enable bit properly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-09-20Only call radeon_dri2_close_screen() if DRI2 was enabled.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-09-20Remove dead variable remain_size_bytes.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-09-20KMS Color Tiling requires xserver which supports EXA_MIXED_PIXMAPS.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-09-17man: note that the list of marketing names is non-exhaustiveAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-09-15update man page with new marking namesAlex Deucher
Note that the driver support all currently shipping asics and the names in the man page are just a sampling. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=40808 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-08-18Convert register ranges for >= r6xx from enums to defines.Michel Dänzer
Avoids lots of "comparison between 'enum <anonymous>' and 'enum <anonymous>'" warnings with newer versions of gcc. See https://bugs.freedesktop.org/show_bug.cgi?id=38238 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-08-17Bail if we're trying to start up in UMS mode on KMS.Michel Dänzer
Ideally, the display manager will start the X server again, and everything will be fine and dandy. But in the worst case, at least we won't hit the hardware behind the KMS driver's back. (This change intentionally makes (ab)use of the fact that Bool is defined as int). Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-08-11video: Don't round up bottom/right edge for clipping source width/height.Michel Dänzer
It's not necessary: If the top/left edge was rounded down, this will be compensated by the subtraction. Worse, if the original source width/height is odd, rounding up may result in reading past the end of the source data. Fixes http://bugs.debian.org/637258 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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