Age | Commit message (Collapse) | Author |
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- KMS only
- Includes full EXA/Xv support
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Use libdrm common surface code so mesa,ddx have same idea
about tiling surface and what their pitch should be and
the alignment constraint.
v2 fix remaining issue add new option to conditionaly enable
v3 fix fbcon copy and r600 exa copy path
v4 fix non tiled path 2D tiling on GPU >= R600, set it to false
as default
v5 adapt to pixel/element size split of libdrm/radeon
v6 update to properly handle falling back to 1d tiled
v6 final fix to tile split value on evergreen and newer
v7 fix default array mode on r6xx, fix height alignment issue
on evergreen
v8 fix tile split value
v9 add stencil tile split support, simplify dri2 for stencil
with evergreen
v10 Try to fix xv path regarding tiling. Adapt to libdrm API
change. Try to fix case where there is no surface which
means non tiled bo.
v11 check for proper libdrm
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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The range passed in is in pixmap coordinates, so the CRTC offset needs to be
added to the clamping limits and subtracted from the clamped range for
pre-AVIVO display engines.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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The clamping could turn a previously non-empty range into an empty one.
Also, start == stop means the range is empty.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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The constants are written directly into a buffer object shared with the
card and we "forget" to swap them. This patch fixes it by doing the swap
in evergreen_set_alu_consts() in-place (ie, it modifies the buffer),
which should be fine with the way we use it in the ddx.
This makes everything work fine on my caicos card on a G5 including some
quik tests with Xv, gnome3 shell, etc...
Thanks a lot to Jerome Glisse for holding my hand through debugging that
(and finding the actual bug).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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On r5xx+, vline is relative to to the viewport, not
the scanlines. Based on initial patch and investigation
from Herbert Pötzl (Bertl) on IRC.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Avoids rendering problems when compute changes this reg.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=39119
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- KMS only
- Includes full EXA/Xv support
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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The rest of the state functions can be shared
with evergreen. I've noted where there are
differences.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- properly set tiling flags for temp surfaces
- fix CB non_disp_tiling bits on evergreen
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Based on 6xx/7xx patches from Cédric Cano.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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We already reset vb_start_op to -1 in the
UMS/KMS ib discard functions.
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=30685
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Note, you also need a drm patch to fix the GPU hangs:
drm/radeon/kms/evergreen: fix gpu hangs in userspace accel code
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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this way we can share the vbo code with const buffers
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Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases. We haven't
tracked down why yet. Might be related to constant
buffer persistence.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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